NDLI: Keynote speaker: Driving innovation in the "post-silicon" world

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2015 28th IEEE International System-on-Chip Conference (SOCC)

2014 27th IEEE International System-on-Chip Conference (SOCC)

2013 IEEE International SOC Conference

2012 IEEE International SOC Conference

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Table of contents

Keynote speaker: Driving innovation in the "post-silicon" world

Plenary speaker: Low power solutions for a smarter future

Plenary speaker: Era of SoCs: What is next?

An energy-efficient level converter with high thermal variation immunity for sub-threshold to super-threshold operation

An on-chip 250 mA 40 nm CMOS digital LDO using dynamic sampling clock frequency scaling with offset-free TDC-based voltage sensor

A better-than-worst-case circuit design methodology using timing-error speculation and frequency adaptation

Variation-and-aging aware low power embedded SRAM for multimedia applications

pbCAM: Probabilistically-banked Content Addressable Memory

“Free” Razor: A novel adaptive voltage scaling low power technique for data path SoC designs

ADPLL variables determinations based on phase noise, spur and locking time

A novel digital loop filter architecture for bang-bang ADPLL

A 1.7GS/s 6-bit Flash A/D converter with distributed offset cancelling sample-and-hold

A 1.62/2.7/5.4Gbps clock and data recovery circuit for DisplayPort 1.2

Gray-level image recognition on a dynamically reconfigurable vision architecture

A read-assist write-back voltage sense amplifier for low voltage-operated SRAMs

Synthesizable delay line architectures for digitally controlled voltage regulators

A novel design flow for a 3D heterogeneous system prototyping platform

An FPGA implementation for a high-speed optical link with a PCIe interface

Invited talk: Noise and mismatch in sub 28nm silicon processes

Reconfigurable RRAM for LUT logic mapping: A case study for reliability enhancement

Limitations of integrating field induced aggregation based fault repair automatons with integrated circuits

Efficient generation of analog circuit models for accelerated mixed-signal simulation

Neural recording system with low-noise analog front-end and comparator-based cyclic ADC

Methodology to determine dominant noise source in a system-on-chip based implantable device

A wide tuning range QCCO based on CMOS active inductors

Evaluation of layout design styles using a quality design metric

Lightweight energy prediction framework for solar-powered wireless sensor networks

Design of near threshold All Digital Delay Locked Loops

A stable chip-ID generating physical uncloneable function using random address errors in SRAM

STT-MRAM memory cells with enhanced on/off ratio

Efficient high-speed current-mode links for network-on-chip performance optimization

Electrical and fluidic microbumps and interconnects for 3D-IC and silicon interposer

Interconnect compression and its benefits for multi-core systems

Ventti: A vertically integrated framework for simulation and optimization of networks-on-Chip

Reconfigurable framework for high-bandwidth stream-oriented data processing

A testability-aware low power architecture

Plenary speaker: Connectivity driven systems: On-chip, off-chip and in-between

Multi-objective optimization of radio-frequency front-ends

Continuous-time single-symbol IR-UWB symbol detection

A 1Gbps FPGA-based wireless baseband MIMO transceiver

Implementation of a network flow lookup circuit for next-generation packet classifiers

Design of a sensor node crypto processor for IEEE 802.15.4 applications

A 55nm 0.5V 128Kb cross-point 8T SRAM with data-aware dynamic supply Write-assist

Low power 6T-SRAM with tree address decoder using a new equalizer precharge scheme

Efficient, snoopless, System-on-Chip coherence

SOLARCAP: Super capacitor buffering of solar energy for self-sustainable field systems

An approach for quantitative optimization of highly efficient dedicated CORDIC macros as SoC building blocks

Workload and task characterization based on operation modes timing analysis

Direction-constrained layer assignment for rectangle escape routing

Schematic-driven physical verification: Fully automated solution for analog IC design

Multi-Clock DFT architecture for interface characterization and power

Optimal power-constrained SoC test schedules with customizable clock rates

Efficient fault emulation using automatic pre-injection memory access analysis

Mutation-analysis driven functional verification of a soft microprocessor

Intellectual property protection and security of SoCs — An embedded tutorial

Neuromorphic computing: A SoC scaling path for the next decades

Exploiting memristive device behavior for emerging digital logic and memory applications

A massive parallel neuromorphic computing model for intelligent text recognition

Memristor in neuromorphic computing

A power-area analysis of NoCs in FPGAs

DVFS-enabled sustainable wireless NoC architecture

Design space exploration for robust power delivery in TSV based 3-D systems-on-chip

A scalable electrical characterization method for inter-strata interconnects in 3-D ICs

Stacking memory architecture exploration for three-dimensional integrated circuit in 3-D PAC

Aging-aware reliable multiplier design

A digital neuromorphic VLSI architecture with memristor crossbar synaptic array for machine learning

A novel flexible foldable systolic architecture FIR filters generator

A sensor-less NBTI mitigation methodology for NoC architectures

Design of a scalable RF microarchitecture for heterogeneous MPSoCs

Design of an NoC with on-chip photonic interconnects using adaptive CDMA links

Design of interlock-free combined allocators for Networks-on-Chip

MAZENOC: Novel approach for fault-tolerant NOC routing

On-chip self-calibrated process-temperature sensor for TSV 3D integration

Calibration of propagation delay of flip-flops

Native-conflict-avoiding track routing for double patterning technology

Variation tolerant self-adaptive clock generation architecture based on a ring oscillator

2011 IEEE International SOC Conference

23rd IEEE International SOC Conference

2009 IEEE International SOC Conference (SOCC)

2008 IEEE International SOC Conference

2007 IEEE International SOC Conference

2006 IEEE International SOC Conference

Proceedings 2005 IEEE International SOC Conference

IEEE International SOC Conference, 2004. Proceedings.

IEEE International [Systems-on-Chip] SOC Conference, 2003. Proceedings.

Keynote speaker: Driving innovation in the "post-silicon" world

Content Provider	IEEE Xplore Digital Library
Author	Meyerson, B.S.
Copyright Year	2012
Description	Author affiliation: Innovation & Global University Relations, IBM Systems and Technology Group (Meyerson, B.S.)
Abstract	For a long time there have been those who postulated the "end of the line" for silicon technology. Invariably, silicon technology survived and thrived following such dire predictions. The fundamental issue behind such predictions was the notion that manufacturing issues such as lithographic pattern definition would cause progress in silicon technology to stall, yet such limits were routinely overcome. However, the laws of physics are not malleable, and we now approach such limits in CMOS. The onset of quantization in highly scaled devices leaves "only" an order of magnitude in device density to work with before limits of classical devices are reached. This talk will explore the coming transition to a "post-silicon" world, where integration, architecture, and numerous scaling independent initiatives will dominate as drivers of IT performance.
Starting Page	1
Ending Page	2
File Size	70176
Page Count	2
File Format	PDF
ISBN	9781467312943
ISSN	21641706
e-ISBN	9781467312950
DOI	10.1109/SOCC.2012.6398342
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2012-09-12
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Content Type	Text

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