NDLI: A low power and low area active clock deskewing technique for sub-90nm technologies

Content Provider	IEEE Xplore Digital Library
Author	Narasimhan, A. Sridhar, R.
Copyright Year	2008
Description	Author affiliation: Dept. of Comput. Sci. & Eng., Univ. at Buffalo (SUNY), Buffalo, NY (Narasimhan, A.; Sridhar, R.)
Abstract	Unintentional clock skew caused by variability can result in degraded and unreliable system performance. In this paper, we present a deskewing technique that continuously senses and compensates for unintentional clock skew. It uses an enhanced skew detector block that detects the skew magnitude in addition to the phase. This helps eliminate the need for complex feedback control, thus reducing the power consumption and the area overhead. Simulation results on a benchmark circuit in 65 nm technology show that the deskewed clock has less than 1 ps skew at clock frequencies of upto 2.5 GHz and 55 ps of input skew. Power consumed and area overhead in the deskew circuit is reduced by greater than 50% and 40% respectively, compared to other techniques. Montecarlo simulation of process variations shows maximum output skew of less than 18 ps, and a standard deviation of 1 mW in power consumed in the deskewing circuit.
Starting Page	179
Ending Page	182
File Size	218725
Page Count	4
File Format	PDF
ISBN	9781424425969
DOI	10.1109/SOCC.2008.4641506
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2008-09-17
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Clocks Delay Timing Voltage control Integrated circuit modeling Video recording Power demand
Content Type	Text
Resource Type	Article

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