NDLI: An independent-gate FinFET SRAM cell for high data stability and enhanced integration density

Content Provider	IEEE Xplore Digital Library
Author	Zhiyu Liu, Tawfik, Sherif A. Kursun, Volkan
Copyright Year	2007
Description	Author affiliation: Department of Electrical and Computer Engineering, University of Wisconsin - Madison, 53706 - 1691, USA (Zhiyu Liu,; Tawfik, Sherif A.; Kursun, Volkan)
Abstract	Data stability of SRAM cells has become an important issue with the scaling of CMOS technology. SRAM arrays are also an important source of leakage in today’s high performance microprocessors. A new six transistor (6T) SRAM cell based on independent-gate (IG) FinFET technology is presented in this paper for simultaneously reducing the active and standby mode power consumption while enhancing the data stability and the integration density. The new IG-FinFET SRAM cell activates only one gate of the data access transistors during a read operation. The disturbance caused by the direct data access mechanism of the standard 6T SRAM cell topology is significantly reduced by dynamically increasing the threshold voltage of the access transistors. All the transistors in the IG-FinFET SRAM cell are sized minimum without producing any data stability concerns. The read static-noise-margin (SNM) of the new circuit is enhanced by up to 2× as compared to the standard tied-gate FinFET SRAM cells. Alternatively, the IG-FinFET SRAM circuit reduces the leakage power and area by up to 51.7% and 10%, respectively, as compared to the standard tied-gate FinFET SRAM circuits sized for comparable data stability in a 32nm FinFET technology.
Starting Page	63
Ending Page	66
File Size	514567
Page Count	4
File Format	PDF
ISBN	9781424415922
DOI	10.1109/SOCC.2007.4545427
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2007-09-26
Publisher Place	Taiwan
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	FinFETs Random access memory CMOS technology MOSFETs Energy consumption Threshold voltage Circuit stability Leakage current Subthreshold current Dielectrics double gate MOSFET Cache memory static noise margin data stability active power standby power
Content Type	Text
Resource Type	Article

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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