NDLI: Digital clock frequency doubler

Please wait, while we are loading the content...

2015 28th IEEE International System-on-Chip Conference (SOCC)

2014 27th IEEE International System-on-Chip Conference (SOCC)

2013 IEEE International SOC Conference

2012 IEEE International SOC Conference

2011 IEEE International SOC Conference

23rd IEEE International SOC Conference

2009 IEEE International SOC Conference (SOCC)

2008 IEEE International SOC Conference

2007 IEEE International SOC Conference

2006 IEEE International SOC Conference

Proceedings 2005 IEEE International SOC Conference

Proceedings. IEEE International SOC Conference (IEEE Cat. No. 05TH8822)

Message from the General Chair

Message From the Technical Program Chair

Program-at-a Glance

List of reviewers

Table of contents

Session quick index

3.48mW 2.4GHz range Frequency Synthesizer Architecture with Two-Point Channel Control for Fast Settling Performance

A Low Jitter Programmable Frequency Synthesizer for 4.25Gbps Serial Link Applications

3.125Gbps Reference-less Clock and Data Recovery using 4X Oversampling

Digital clock frequency doubler

Power minimization of rotary clock design

Thermal-aware mapping and placement for 3-D NoC designs

An IR drop-driven placer for standard cells in a SOC design

Combined simulator statistics and block code sampling to study performance enhancement of microarchitecture

A CMOS Voltage Reference with Temperature Sensor using Self-PTAT Current Compensation

Hybrid Voltage and Current References Based on Double ZTC Points

Automatic gain control circuit for power line communication application

CMOS SoC for irrigation control

A Flow Graph Technique for DFT Controller Modification

Testing system-on-a-chip using artificial immune system

Improving Error Resilience for Compressed Test Sets by Don't Care Assignment

Hybrid test data compression technique for SOC scan testing

A low jitter delay-locked loop with a realignment duty cycle corrector

1.8-V 10-GHZ ring VCO design using 0.18-μm CMOS technology

A CMOS RF tuning wide-band bandpass filter for wireless applications

Reliability-aware floorplanning for 3D circuits

Synchronous latency-insensitive design for multiple clock domain

Design study of (2 x 2) core architecture for matrix multiplications via programmable graph architecture

Constraint-based Code mapping for heterogeneous Chip multiprocessors

Efficient VLSI Architecture for Real-Time Motion Estimation in Advanced Video Coding

Architecture and design methodology for synthesizable reconfigurable array targeting wireless system-on-chip applications

Precharged SRAM cell for ultra low-power on-chip cache

GPSDVS: An improved task-based dynamic voltage scaling scheme for general-purpose systems

A novel five-transistor (5T) sram cell for high performance cache

Improved memory strategy for logmap turbo decoders

Accurate Simulation Environment for Signal Isolation in Mixed-Signal Design

Support for multiprocessor synchronization and resource sharing in system-on-programmable chips with softcores

Mapping of partial reconfigurable data flows to Xilinx FPGAs

A Low Power Heterogenous Reconfigurable Architecture For Embedded Generic Finite State Machines

FPGA-based vector processor for algebraic equation solvers

Novel VLSI architecture of motion estimation for H.264 standard

Integrated assignment of registers and functional units for heterogeneous vliw-architectures

Simultaneous memory and bus partitioning for SoC architectures

Resource allocation methodology for the segmented bus platform

System Level Design Methodology for System On Chips using Multi-Threaded Graphs

Gigascale ASIC/SoC design using wave-pipelined multiplexed (WPM) routing

A New Breed of Power-Aware Hybrid Shifters

Adaptive MTCMOS for dynamic leakage and frequency control using variable footer strength

Shifted Leakage Power Characteristics of Dynamic Circuits Due to Gate Oxide Tunneling

Workload Clustering for Increasing Energy Savings on Embedded MPSoCs

Design and implementation of interface circuitry for cmos-based saw gas sensors

DG-SRAM: a low leakage memory circuit

Novel 7T sram cell for low power cache design

On-Chip Memory Management for Embedded MpSoC Architectures Based on Data Compression

CMOS passive RFID transponder with read-only memory for low cost fabrication

A band-switching wide-band CMOS LC QVCO for multi-standard applications

A 2 GHz and 5GHz dual-band direct conversion RF frontend for multi-standard applications

Limiting amplifiers for next-generation multi-channel optical I/0 interfaces in SoCs

Dynamic fraction control bus: new SOC on-chip communication architecture design

Resistive Loss and Trans-Impedance Characterization of Nonlinear Transmission Lines on CMOS SOI Substrate

Designing for signal integrity in wave-pipelined SOC global interconnects

An improved implementation method of AHB BusMatrix

Effective IP reuse for high quality SOC design

Virtual Hierarchical Design Representations for Distributed Optimization of Multi-Million Gate Designs

Including Power Supply Variations into Static Timing Analysis: Methodology and Flow

Operating system support for dynamically reconfigurable SoC architectures

Online-adaptive Reconfigurable Hardware Architecture and Runtime Environment

A highly reconfigurable computing array: DSP plane of a 3D heterogeneous SoC

A Power Efficient Reconfigurable Max-Log-MAP Turbo Decoder for Wireless Communication Systems

A Clock Isolation Method For Complex SoC Designs

A 10 Gb/s Wide-Band Current-Mode Logic I/O Interface for High-Speed Interconnect in 0.18μm CMOS Technology

Bus Buffer Evaluation of Different Arbitration Algorithms

Novel secret-key IPR protection in FPGA environment

FPGA implementation of the "pyramids" block cipher

A hierarchically-controlled SIMD machine for 2D DCT on FPGAs

Design and implementation of a shared buffer architecture for a gigabit Ethernet packet switch

Hardware Design of Sphere Decoding for MIMO Systems

Design and implementation of phase correlation based motion estimator

Differential Pass Transistor Pulsed Latch

A High-Performance Router Design for VDSM NoCs

A novel multiplier for high-speed applications

On-Chip Power Noise Reduction Techniques in High Performance SoC-Based Integrated Circuits

I Models and Tools for the Dynamic Reconfiguration of FPGAs

Serial RapidlO: Benefiting System Interconnects

Digital signal processors for communications, video infrastructure, and audio

Standards-compliant IP-based ASIC and SoC design

High-Performance On-Chip Interconnect Circuit Technologies for sub-65nm CMOS

IEEE International SOC Conference, 2004. Proceedings.

IEEE International [Systems-on-Chip] SOC Conference, 2003. Proceedings.

Digital clock frequency doubler

Content Provider	IEEE Xplore Digital Library
Author	Wadhwa, S.K. Khan, Q.A. Kulbhushan Misri Deeya Muhury
Copyright Year	2005
Description	Author affiliation: Freescale Semicond. India Pvt. Ltd., Bangalore (Wadhwa, S.K.; Khan, Q.A.; Kulbhushan Misri; Deeya Muhury)
Abstract	A digital clock frequency doubler capable of handling large variation in input duty cycle and PVT (process, voltage and temperature) is presented. Unlike the conventional clock frequency doublers, the proposed circuit doesn't require 50% duty cycle for doubling the input clock frequency and consumes lower silicon area. A digital algorithm is used to generate output frequency and an inbuilt PVT compensation mechanism ensures good frequency stability if there is any change in PVT. The circuit has been designed in 90nm CMOS process with input frequency range of 10MHz to 30MHz and silicon results show less than 0.2% of average frequency error
Sponsorship	IEEE Circuits and Syst. Soc
Starting Page	15
Ending Page	18
File Size	1841367
Page Count	4
File Format	PDF
ISBN	0780392647
DOI	10.1109/SOCC.2005.1554445
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2005-09-25
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Clocks Frequency Phase locked loops Silicon Costs Jitter Voltage Temperature Circuit stability CMOS process
Content Type	Text
Resource Type	Article

Central Library (ISO-9001:2015 Certified)
Indian Institute of Technology Kharagpur
Kharagpur, West Bengal, India | PIN - 721302

See location in the Map
03222 282435
Mail: support@ndl.gov.in

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in