NDLI: A highly reconfigurable computing array: DSP plane of a 3D heterogeneous SoC

Content Provider	IEEE Xplore Digital Library
Author	Jain, V.K. Bhanja, S. Chapman, G.H. Doddannagari, L.
Copyright Year	2005
Description	Author affiliation: South Florida Univ., Tampa, FL, USA (Jain, V.K.; Bhanja, S.)
Abstract	A 3D heterogeneous system on a chip using a stack of planes has recently been proposed. While the sensors are located on the top plane, the other planes provide for analog processing, digital signal processing, and wireless communication. This paper focuses on a reconfigurable computing array for its DSP plane. The advantages of such an approach are high performance, small area and low power compared to FPGAs, and greater flexibility over ASICs. The authors presented the reconfigurable J-platform, which employs coarse-grain VLSI cells with high functionality, performance, and reconfigurability. These include a universal nonlinear (UNL) cell, an extended multiply accumulate (MA/spl I.bar/PLUS) cell, and a data-fabric (DF) cell. The coarse-grain approach has the benefits of reduced external interconnect, much reduced design time, and manageable testability. The paper discusses these cells, including a new concept, namely multi-granularity. The methodology for mapping algorithms is illustrated by two important examples, FIR filtering of signals and images and the independent component analysis (ICA) algorithm. Finally, the paper discusses the issue of defect tolerance, which is critical in attaining reasonable yields making chip manufacture feasible.
Sponsorship	IEEE Circuits and Syst. Soc
Starting Page	243
Ending Page	246
File Size	3080886
Page Count	4
File Format	PDF
ISBN	0780392647
DOI	10.1109/SOCC.2005.1554503
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2005-09-25
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Digital signal processing Digital signal processing chips Signal processing algorithms Filtering algorithms Finite impulse response filter Independent component analysis System-on-a-chip Wireless communication Field programmable gate arrays Very large scale integration
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
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9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

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