NDLI: High speed mixed analog/digital PRML architecture for optical data storage system

Content Provider	IEEE Xplore Digital Library
Author	Konakov, M. Jae-Wook Lee Junghyun Lee Eun-Jin Ryu Eingseob Cho Jungeun Lee Hyunsu Chae Jeongwon Lee
Copyright Year	2004
Description	Author affiliation: i-Networking Lab., Samsung Adv. Inst. of Technol., Kyunggi-Do, South Korea (Konakov, M.; Jae-Wook Lee; Junghyun Lee; Eun-Jin Ryu; Eingseob Cho; Jungeun Lee; Hyunsu Chae; Jeongwon Lee)
Abstract	New mixed analog/digital PRML (partial response maximum likelihood) architecture for the optical drive system is presented. In order to realize high speed, low power and low cost solution, new data and clock recovery circuits are proposed. The proposed architecture is based on the efficient combination of digital and analog circuits to provide high speed and low power data detection for optical data storage system. The presented circuit shows increased operating speed by 67%, reduced power consumption by 28% and area by 42%, therefore it provides high speed, low power and low cost SOC solution for the future optical drive system. A test chip produced is fabricated using 0.18 /spl mu/m CMOS technology and the product has been proved to demonstrate the performance of the proposed architecture.
Sponsorship	IEEE Circuits and Syst. Soc
Starting Page	209
Ending Page	212
File Size	288004
Page Count	4
File Format	PDF
ISBN	0780384458
DOI	10.1109/SOCC.2004.1362410
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2004-09-12
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	High speed optical techniques Data storage systems Costs CMOS technology Maximum likelihood detection Clocks Analog circuits Optical detectors Energy consumption Circuit testing
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

A CMOS analog timing recovery circuit for PRML detectors

The effect of scaling upto future analog/digital systems

A new architecture for area and power efficient, high conversion rate successive approximation ADCs

A CMOS analog timing recovery circuit for 180 Mb/s PRML detectors

Viterbi detector architecture for high speed optical storage

1.2 micron, high speed, high density CMOS analog library

A comparator-based I/sub DDQ/ testing of CMOS analog and mixed-signal integrated circuits

A 10-Gb/s CMOS clock and data recovery circuit with an analog phase interpolator

Block-Oriented Test-Strategy for Analog Circuits

High speed mixed analog/digital PRML architecture for optical data storage system

Similar Documents

A CMOS analog timing recovery circuit for PRML detectors

The effect of scaling upto future analog/digital systems

A new architecture for area and power efficient, high conversion rate successive approximation ADCs

A CMOS analog timing recovery circuit for 180 Mb/s PRML detectors

Viterbi detector architecture for high speed optical storage

1.2 micron, high speed, high density CMOS analog library

A comparator-based I/sub DDQ/ testing of CMOS analog and mixed-signal integrated circuits

A 10-Gb/s CMOS clock and data recovery circuit with an analog phase interpolator

Block-Oriented Test-Strategy for Analog Circuits

High speed mixed analog/digital PRML architecture for optical data storage system