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Novel ultra low-leakage power circuit techniques and design algorithms in PD-SOI for sub-1 V applications
| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Das, K.K. Brown, R.B. |
| Copyright Year | 2002 |
| Description | Author affiliation: Dept. of Electr. Eng. & Comput. Sci., Michigan Univ., Ann Arbor, MI, USA (Das, K.K.; Brown, R.B.) As supply voltage and technology are scaled, leakage power becomes significant in CMOS ICs. This paper proposes and analyzes new circuit styles in PD-SOI technology which reduce standby power in the sub-1 V regime by over three orders of magnitude while maintaining circuit speed with minimal overhead. Simulation results obtained using process parameters from an IBM 0.13 /spl mu/m PD-SOI technology show considerable improvement over previously proposed methods as supply voltage is scaled to 0.5 V. It also proposes a definitive design guideline for implementing such schemes. |
| Sponsorship | IEEE Electron Devices Soc |
| Starting Page | 88 |
| Ending Page | 90 |
| File Size | 210491 |
| Page Count | 3 |
| File Format | |
| ISBN | 0780374398 |
| DOI | 10.1109/SOI.2002.1044429 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2002-10-07 |
| Publisher Place | USA |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Silicon on insulator technology CMOS integrated circuits SPICE Leakage currents Integrated circuit design |
| Content Type | Text |
| Resource Type | Article |
