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History effect characterization in PD-SOI CMOS gates
| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Casu, M.R. Flatresse, P. |
| Copyright Year | 2002 |
| Description | Author affiliation: Politecnico di Torino, Italy (Casu, M.R.) Partially depleted SOI CMOS gates with floating body exhibit variable propagation delays because of the history effect. In this paper we address the problem of how to find the steady-state in a CMOS gate without resorting to huge computer resources. Moreover, a simple method for the evaluation of delay upper and lower bounds is described. |
| Sponsorship | IEEE Electron Devices Soc |
| Starting Page | 62 |
| Ending Page | 63 |
| File Size | 139993 |
| Page Count | 2 |
| File Format | |
| ISBN | 0780374398 |
| DOI | 10.1109/SOI.2002.1044417 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2002-10-07 |
| Publisher Place | USA |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Silicon Silicon on insulator technology CMOS integrated circuits Integrated circuit modeling |
| Content Type | Text |
| Resource Type | Article |
