NDLI: Modeling and simulation of a fault tolerant ATM switching architecture

Content Provider	IEEE Xplore Digital Library
Author	Anan, M. Guizani, M.
Copyright Year	2000
Abstract	Multistage interconnection networks (MINs) have been proposed as the switching fabrics for B-ISDN. With the throughput requirement of the packet switches exceeding several gigabits/sec, it becomes important to make them fault tolerant. To provide fault tolerance and improve network performance, a new fault-tolerant, self-routing, and high performance switching architecture for ATM networks based on MINs is proposed. It consists of two closely linked Banyan networks. Links are provided at every stage to allow cells to transfer to and from each plane. The performance and the reliability of the proposed architecture is compared to the other networks. The proposed network has low cell loss rate probabilities than other networks for both fault-free and faulty environments. Routing is kept simple as in basic MINs. Furthermore, the proposed switch architecture is modular in its design making it ideal for VLSI implementation.
Starting Page	42
Ending Page	47
File Size	66420
Page Count	6
File Format	PDF
ISBN	0769505988
ISSN	1080241X
DOI	10.1109/SIMSYM.2000.844899
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2000-04-16
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Fault tolerance Asynchronous transfer mode Switches Multiprocessor interconnection networks Fabrics B-ISDN Throughput Packet switching Routing Very large scale integration
Content Type	Text
Resource Type	Article

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