NDLI: Semi-classical ensemble Monte Carlo simulator using innovative quantum corrections for nano-scale n-channel FinFETs

Content Provider	IEEE Xplore Digital Library
Author	Crum, D.M. Valsaraj, A. Register, L.F. Banerjee, S.K.
Copyright Year	2014
Description	Author affiliation: Dept. of Electr. & Comput. Eng., Univ. of Texas at Austin, Austin, TX, USA (Crum, D.M.; Valsaraj, A.; Register, L.F.; Banerjee, S.K.)
Abstract	We present a three-dimensional semi-classical ensemble Monte Carlo device simulator with novel quantum corrections. The simulator includes a beyond-Fermi treatment of Pauli-Exclusion-blocked scattering, and a valley-dependent treatment of various quantum confinement effects. Quantum corrections to the potential are used not only to model redistribution of carriers in real space, but also to model altered energy valley offsets and associated redistribution of carriers in k-space, and quantum-confined scattering rates, including a new approach to model surface roughness scattering. We illustrate the capabilities of the simulator using different levels of modeling, with an emphasis on modeling nano-scale FinFETs with degenerate carrier populations, including III-V devices.
Starting Page	109
Ending Page	112
File Size	985752
Page Count	4
File Format	PDF
ISBN	9781479952878
ISSN	19461569
e-ISBN	9781479952885
DOI	10.1109/SISPAD.2014.6931575
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2014-09-09
Publisher Place	Japan
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Scattering FinFETs Monte Carlo methods Silicon Potential well Logic gates device modeling FinFET Monte Carlo quantum-confinement surface roughness scattering III-V n-MOS scaling degenerate semiconductors
Content Type	Text
Resource Type	Article

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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