NDLI: Simulation of the circuit performance impact of lithography in nanoscale semiconductor manufacturing

Content Provider	IEEE Xplore Digital Library
Author	Munkang Choi Milor, L. Capodieci, L.
Copyright Year	2003
Description	Author affiliation: Sch. of Electr. & Comput. Eng., Georgia Inst. of Technol., Atlanta, GA, USA (Munkang Choi; Milor, L.)
Abstract	With nanoscale semiconductor technology, circuit performance is increasingly influenced by details of the manufacturing process. An increasing number of manufacturing features, which are not included in standard design tools, affect both circuit performance and yield. One source of circuit performance degradation is lithography imperfections. Therefore, we need to simulate how lithography imperfections impact circuit performance. Such imperfections include the proximity effect, lens aberrations, and flare. These imperfections in lithography impact circuit timing. This paper introduces a method to incorporate the proximity effect, lens aberrations, and flare in timing simulation. Our method involves expanding and revising the cell library by considering optical effects. ISCAS benchmark circuits are used to evaluate the circuit performance impact of each optical effect.
Sponsorship	IEEE Electron Devices Soc
Starting Page	219
Ending Page	222
File Size	353840
Page Count	4
File Format	PDF
ISBN	0780378261
DOI	10.1109/SISPAD.2003.1233676
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2003-09-03
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Circuit simulation Circuit optimization Lithography Virtual manufacturing Semiconductor device manufacture Proximity effect Lenses Timing Manufacturing processes Degradation
Content Type	Text
Resource Type	Article

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