NDLI: A Smart Sampling Scheduling and Skipping Simulator and its evaluation on real data sets

Content Provider	IEEE Xplore Digital Library
Author	Yugma, C. Dauzere-Peres, S. Rouveyrol, J. Vialletelle, P. Pinaton, J. Relliaud, C.
Copyright Year	2011
Description	Author affiliation: LFoundry, Zone industrielle Rousset, 84 Avenue Olivier Perroy, 13790, France (Relliaud, C.) \|\| STMicroelectronics, 850 rue Jean Monnet, 38926 Crolles cedex, France (Vialletelle, P.) \|\| STMicroelectronics, Zone Industrielle Rousset, 13106 cedex, France (Pinaton, J.) \|\| École des Mines de Saint- Étienne, Centre Microélectronique de Provence, Site Georges Charpak, 880 Avenue de Mimet, Gardanne F-13541, France (Yugma, C.; Dauzere-Peres, S.; Rouveyrol, J.)
Abstract	As modern manufacturing technology progresses, measurement tools become scarce resources since more and longer control operations are required. It thus becomes critical to decide whether a lot should be measured or not in order to get as much information as possible on production tools or processes, and to avoid ineffective measurements. To minimize risks and optimize measurement capacity, a smart sampling algorithm has been proposed to efficiently select and schedule production lots on metrology tools. This algorithm and others have been embedded in a simulator called “Smart Sampling Scheduling and Skipping Simulator” (S5). The characteristics of the simulator will be presented. Simulations performed on several sets of instances from three different semiconductor manufacturing facilities (or fabs) will be presented and discussed. The results show that, by using smart sampling, it is possible to drastically improve various factory performance indicators when compared to current fab sampling.
Starting Page	1903
Ending Page	1912
File Size	494337
Page Count	10
File Format	PDF
ISBN	9781457721083
ISSN	08917736
e-ISBN	9781457721090
e-ISBN	9781457721076
DOI	10.1109/WSC.2011.6147904
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2011-12-11
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Semiconductor device measurement Metrology Job shop scheduling Current measurement Time measurement Production facilities
Content Type	Text
Resource Type	Article
Subject	Modeling and Simulation Computer Science Applications Software

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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A smart sampling scheduling and skipping simulator and its evaluation on real data sets.

A SMART SAMPLING SCHEDULING AND SKIPPING SIMULATOR AND ITS EVALUATION ON REAL DATA SETS

A smart sampling scheduling and skipping simulator and its evaluation on real data sets

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