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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Zhugen Zhou Rose, O. |
| Copyright Year | 2010 |
| Description | Author affiliation: Institute of Applied Computer Science, Dresden University of Technology, 01187, GERMANY (Zhugen Zhou; Rose, O.) |
| Abstract | In this paper, a pull/push concept is proposed in order to balance toolgroup workload in a wafer fab. This is accomplished by using a so-called WIP Control Table. Each upstream toolgroup maintains a WIP Control Table which contains current WIP information of downstream toolgroups such as target WIP, actual WIP and WIP difference. In case of lot move in/out and tool status change, the WIP Control Table is updated. Therefore, the upstream toolgroup is able to detect WIP distribution and pull request of downstream toolgroups dynamically, then push optimal lots with consideration of lot status and local tool constraint to the downstream toolgroup which runs short of WIP. The simulation results demonstrate that the proposed pull/push concept is superior over First-in-First-out (FIFO) and Operation Due Date (ODD) with regard to average cycle time and on time delivery. |
| Starting Page | 2516 |
| Ending Page | 2522 |
| File Size | 5906840 |
| Page Count | 7 |
| File Format | |
| ISBN | 9781424498666 |
| ISSN | 15584305 |
| e-ISBN | 9781424498659 |
| DOI | 10.1109/WSC.2010.5678947 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2010-12-05 |
| Publisher Place | USA |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Simulation Semiconductor device modeling Loading Load modeling Dispatching Acceleration Data models |
| Content Type | Text |
| Resource Type | Article |
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