NDLI: High-Q inductors and transmission lines on 20 /spl Omega/.cm Si using wafer-level packaging technology

Content Provider	IEEE Xplore Digital Library
Author	Carchon, G. Xiao Sun De Raedt, W.
Copyright Year	2003
Description	Author affiliation: IMEC, Heverlee, Belgium (Carchon, G.; Xiao Sun; De Raedt, W.)
Abstract	High Q on-chip inductors and low loss on-chip interconnects and transmission lines are an important roadblock for the further development of Si-based technologies at RF and microwave frequencies. In this paper, inductors are realised on 20 /spl Omega/.cm Si wafers using thin-film Wafer-Level Packaging (WLP) technology: two low K benzo-cyclobutene (BCB, /spl epsiv//sub r/=2.65) dielectric layers and a thick Cu interconnect layer are deposited on floating Si substrates. Inductors with 5/spl mu/m minimum lines and spaces are demonstrated for a 5/spl mu/m thick Cu layer, hereby leading to very compact and high performance inductors: maximum Q-factors of 25 have been obtained for inductances in the range of 1 to 5 nH. It is shown how Q-factor and resonance frequency vary as a function of the inductor layout parameters and the thickness of the BCB and Cu layers. The realised 50 /spl Omega/ CPW lines (lateral dimension of 40 /spl mu/m) have a measured loss of only 0.2 dB/mm@25 GHz. A good agreement between measured and simulated performance has been obtained.
Sponsorship	IEEE Microwave Theory & Tech. Soc. Eur. Microwave Assoc. NASA Glenn Res. Center DaimlerChrysler AG Technische Univ. Muchen
Starting Page	111
Ending Page	114
File Size	246544
Page Count	4
File Format	PDF
ISBN	0780377877
DOI	10.1109/SMIC.2003.1196682
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2003-04-11
Publisher Place	Germany
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Transmission lines Wafer scale integration Thin film inductors Space technology Dielectric substrates Q factor Propagation losses Microwave technology Radio frequency Microwave frequencies
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

Wafer-level packaging technology for extended global wiring and inductors

High-Q RF inductors on standard silicon realized using wafer-level packaging techniques

Wafer level packaging solution for high performance microwave inductors on Si substrates

High-Q on-chip inductors using thin-film wafer level packaging technology demonstrated on a 90 nm RF-CMOS 5 GHz VCO

Analysis of high-Q on-chip inductors realized by wafer-level packaging techniques

A wafer-level interposer based microwave circuit and system integration technology

A 5.2 GHz CMOS Low Noise Amplifier with High-Q Inductors Embedded in Wafer-Level Chip-Scale Package

Wafer-level packaging technology for high-Q on-chip inductors and transmission lines

Development of an organic wafer-level packaging platform for highly integrated RF transceivers

High-Q inductors and transmission lines on 20 /spl Omega/.cm Si using wafer-level packaging technology

Similar Documents

Wafer-level packaging technology for extended global wiring and inductors

High-Q RF inductors on standard silicon realized using wafer-level packaging techniques

Wafer level packaging solution for high performance microwave inductors on Si substrates

High-Q on-chip inductors using thin-film wafer level packaging technology demonstrated on a 90 nm RF-CMOS 5 GHz VCO

Analysis of high-Q on-chip inductors realized by wafer-level packaging techniques

A wafer-level interposer based microwave circuit and system integration technology

A 5.2 GHz CMOS Low Noise Amplifier with High-Q Inductors Embedded in Wafer-Level Chip-Scale Package

Wafer-level packaging technology for high-Q on-chip inductors and transmission lines

Development of an organic wafer-level packaging platform for highly integrated RF transceivers

High-Q inductors and transmission lines on 20 /spl Omega/.cm Si using wafer-level packaging technology