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Content Provider | IEEE Xplore Digital Library |
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Author | Zhiyong He Roy, S. Fortier, P. |
Copyright Year | 2007 |
Description | Author affiliation: Laval Univ., Quebec (Zhiyong He; Roy, S.; Fortier, P.) |
Abstract | This paper discusses high-performance code construction and high-speed encoder and decoder designs for low density parity check (LDPC) codes. Thanks to their nice structures, LDPC codes constructed from shifted identity matrices have been emphasized. Several techniques in code constructions have been proposed to lower the bit error floor down to $10^{-10}.$ Characterized by a parity check matrix in a triangular plus dual-diagonal form, these structured LDPC codes can be encoded in linear time using a layered encoding algorithm. To increase the throughput of decoders, a joint row-column decoding algorithm has been proposed and parallel decoding architectures have been used. The implementation results into field programmable gate array (FPGA) devices indicate that the encoder for these high-performance LDPC codes attains a throughput of up to 115 Gbits/sec and the decoder attains a throughput of up to 1 Gbits/sec. The proposed codes are suitable for high-speed and high-performance applications which demand relatively low error floor, including application in broadband wireless networks. |
Starting Page | 173 |
Ending Page | 176 |
File Size | 325616 |
Page Count | 4 |
File Format | |
ISBN | 1424414482 |
DOI | 10.1109/ISSSE.2007.4294441 |
Language | English |
Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
Publisher Date | 2007-07-30 |
Publisher Place | Canada |
Access Restriction | Subscribed |
Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
Subject Keyword | Parity check codes Wireless networks Floors Iterative decoding Code standards Bit error rate Encoding Throughput Field programmable gate arrays Digital video broadcasting |
Content Type | Text |
Resource Type | Article |
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