NDLI: Co-Simulation of SPICE Netlists and VHDL-AMS Models via a Simulator Interface

Content Provider	IEEE Xplore Digital Library
Author	Frank, F. Weigel, R.
Copyright Year	2007
Description	Author affiliation: Univ. of Erlangen-Nuremberg, Erlangen (Frank, F.; Weigel, R.)
Abstract	This paper addresses a method for simulator coupling allowing a transient time simulation of SPICE and the mixed-signal language VHDL-AMS within one simulation process. To this end, an interface between the two simulators SLSim and SMASH has been developed that links the slave simulator to the master process during runtime. Both simulator cores work independently of each other and the synchronization, which means data exchange, is done at adaptively calculated points in time. Since a mixed-signal simulator consists of an analog and a logic algorithm which are stepped independently through time, synchronization not only means data exchange between the both simulators, but also data exchange between the analog and the logic part of the VHDL-AMS simulator. Due to that, special attention has to be given to the synchronization mechanisms of the simulator interface. The functionality of the co-simulation will be shown by using examples from the field of automotive EMC simulation.
Starting Page	75
Ending Page	78
File Size	245421
Page Count	4
File Format	PDF
ISBN	1424414482
DOI	10.1109/ISSSE.2007.4294417
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2007-07-30
Publisher Place	Canada
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	SPICE Circuit simulation Electromagnetic compatibility Master-slave Transient analysis Logic Automotive engineering Equivalent circuits Integrated circuit modeling Analytical models automotive EMC simulation VHDL-AMS circuit simulation
Content Type	Text
Resource Type	Article

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