NDLI: Reconfigurable multiple constant multiplication using minimum adder depth

Content Provider	IEEE Xplore Digital Library
Author	Faust, M. Gustafsson, O. Chip-Hong Chang
Copyright Year	2010
Description	Author affiliation: Centre for High Performance Embedded Systems, Nanyang Technological University, Singapore (Faust, M.; Chip-Hong Chang) \|\| Department of Electrical Engineering, Linköping University, SE-581 83, Sweden (Gustafsson, O.)
Abstract	The problem of reconfigurable multiple constant multiplication (ReMCM) is about finding an cost-effective network of shifts, additions, subtractions, and multiplexers to implement the multiplication of a single input variable with one out of several sets of coefficients. Most previous publications only focus on the problem with a single output, whereas the algorithm proposed here solves a multiple output ReMCM problem using a adder-graph based minimal logic depth approach. The use of minimal logic depth restricts the length of critical path and it was shown in previous work that minimum depth MCM is advantageous in terms of power consumption. The use of a adder-graph heuristic gives more possibilities for adder formation to reduce the total number of adders and multiplexers. For the polyphase decimation filters, the relation between filter length and decimation factor has been shown to have a influence on the implementation cost. Experimental results showed that a ReMCM can be implemented with up to 38% less area for decimation factor of 8 than a parallel implementation of the polyphase subfilters, while the single output problems can also be solved with results comparable to the known algorithms.
Starting Page	1297
Ending Page	1301
File Size	242096
Page Count	5
File Format	PDF
ISBN	9781424497225
ISSN	10586393
e-ISBN	9781424497218
DOI	10.1109/ACSSC.2010.5757741
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2010-11-07
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Adders Finite impulse response filter Algorithm design and analysis Complexity theory Optimization Multiplexing Signal processing algorithms
Content Type	Text
Resource Type	Article
Subject	Signal Processing Computer Networks and Communications

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4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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