NDLI: Efficient high-speed quasicyclic LDPC decoder architecture

Content Provider	IEEE Xplore Digital Library
Author	Zhang, Y. Wang, Z. Parhi, K.K.
Copyright Year	2004
Description	Author affiliation: Dept. of Electr. & Comput. Eng., Minnesota Univ., Minneapolis, MN, USA (Zhang, Y.)
Abstract	This paper studies load imbalance problem in the two stages of belief propagation decoding algorithm for LDPC codes and redistributes computational load between two stages. To further reduce the critical path delay, new look-up-tables (LUT) are developed to replace both conventional LUTs and data format transformation blocks. The adder trees are also reorganized for speed. This novel approach can reduce the critical path delay by 41.0% with negligible increase in the logic core size. This paper also exploits the similarity between these two stages and derives an area efficient design that remaps the functional units for these two stages onto the same hardware, which can reduce the logic core size by 10.2% and reduce the critical path delay by 16.2%.
Starting Page	540
Ending Page	544
File Size	665908
Page Count	5
File Format	PDF
ISBN	0780386221
DOI	10.1109/ACSSC.2004.1399191
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2004-11-07
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Parity check codes Table lookup Hardware Iterative decoding Belief propagation Delay Chromium Logic Character generation Computer architecture
Content Type	Text
Resource Type	Article

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