NDLI: Energy minimization of a pipelined processor using a low voltage pipelined cache

Content Provider	IEEE Xplore Digital Library
Author	Park, J.C. Mooney III, V.J. Palem, K. Kyu-won Choi
Copyright Year	2002
Description	Author affiliation: Sch. of Electr. & Comput. Eng., Georgia Inst. of Technol., Atlanta, GA, USA (Park, J.C.; Mooney, V.J., III; Palem, K.; Kyu-won Choi)
Abstract	A cache is a power-hungry component in a processor. Therefore, a reduction in cache energy can have a significant impact on overall processor energy consumption. In this paper, we propose a new energy minimization technique for a pipelined processor using a low voltage pipelined cache. We consider a case where a pipelined cache is not required but is used nonetheless, enabling the cache supply voltage to be lowered. Using this method, five benchmarks show that power consumption is reduced by 24.85% at a cost of an average increase in execution time of 15.35% resulting in an average overall energy reduction of 13.33%.
Starting Page	67
Ending Page	73
File Size	509423
Page Count	7
File Format	PDF
ISBN	0780375769
ISSN	10586393
DOI	10.1109/ACSSC.2002.1197151
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2002-11-03
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Low voltage Circuits Energy consumption Costs Pipeline processing Frequency Power engineering computing Power engineering and energy Minimization Embedded system
Content Type	Text
Resource Type	Article
Subject	Signal Processing Computer Networks and Communications

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

Energy Minimization of a Pipelined Processor (2002)

A DVS-based pipelined reconfigurable instruction memory

Custom instruction filter cache synthesis for low-power embedded systems

ROBTIC: An On-chip Instruction Cache Design for Low Power Embedded Systems

Reducing power dissipation in pipelined accumulators

Low-power FIR digital filters using residue arithmetic

Power analysis and low-power scheduling techniques for embedded DSP software

Synthesis for variable pipelined function units

Loop Detection for Energy-Aware High Performance Embedded Processors

Energy minimization of a pipelined processor using a low voltage pipelined cache

Similar Documents

Energy Minimization of a Pipelined Processor (2002)

A DVS-based pipelined reconfigurable instruction memory

Custom instruction filter cache synthesis for low-power embedded systems

ROBTIC: An On-chip Instruction Cache Design for Low Power Embedded Systems

Reducing power dissipation in pipelined accumulators

Low-power FIR digital filters using residue arithmetic

Power analysis and low-power scheduling techniques for embedded DSP software

Synthesis for variable pipelined function units

Loop Detection for Energy-Aware High Performance Embedded Processors

Energy minimization of a pipelined processor using a low voltage pipelined cache