NDLI: Testability improvement in high-level synthesis through reconvergence reduction

Content Provider	IEEE Xplore Digital Library
Author	Harris, I.G. Orailoglu, A.
Copyright Year	1995
Description	Author affiliation: Dept. of Comput. Sci. & Eng., California Univ., San Diego, La Jolla, CA, USA (Harris, I.G.; Orailoglu, A.)
Abstract	Justification of multiple circuit lines in automatic test pattern generation (ATPG) is exponential in complexity in the presence of reconvergent fanout. Reconvergent fanout consequently is a chief source of increased complexity in the ATPG process. Reconvergence also degrades the pseudo-random test by producing correlation between inputs of the same combinational logic block. Consideration of reconvergence during synthesis can result in its elimination at minimal area or performance cost. The high regularity of DSP architectures facilitates reconvergence reduction, when, it is addressed during synthesis. We present a design-for-testability approach to remove reconvergence during high-level synthesis. We have developed a method for estimating the degree of reconvergence, based on an estimate of the existence of paths between each pair of hardware units. We have designed and implemented scheduling and binding algorithms which use the proposed reconvergence estimate to consistently direct synthesis to RTL datapaths with reduced reconvergent fanout. The experimental results shown demonstrate the effectiveness of the proposed methodology.
Starting Page	199
Ending Page	203
File Size	599545
Page Count	5
File Format	PDF
ISBN	0818673702
ISSN	10586393
DOI	10.1109/ACSSC.1995.540540
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1995-10-30
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	High level synthesis Automatic test pattern generation Circuit testing Logic testing Degradation Costs Digital signal processing Hardware Algorithm design and analysis Scheduling algorithm
Content Type	Text
Resource Type	Article
Subject	Signal Processing Computer Networks and Communications

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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