NDLI: Power optimization of a reconfigurable FIR-filter

Content Provider	IEEE Xplore Digital Library
Author	Bruce, H. Veljanovski, R. Owall, V. Singh, J.
Copyright Year	2004
Description	Author affiliation: Dept. of Electroscience, Lund Inst. of Technol., Sweden (Bruce, H.)
Abstract	This paper describes power optimization techniques applied to a reconfigurable digital finite impulse response (FIR) filter used in a Universal Mobile Telephone Service (UMTS) mobile terminal. Various methods of optimization for implementation were combined to achieve low cost in terms of power consumption. Each optimization method is described in detail and is applied to the reconfigurable filter. The optimization methods have achieved a 78.8% reduction in complexity for the multipliers in the FIR structure. A comparison of synthesized RTL models of the original and the optimized architectures resulted in a 27% reduction in look-up tables when targeted for the Xilinx Virtex II Pro field programmable gate array (FPGA). An automated method for transformation of coefficient multipliers into bit-shifts is also presented.
Sponsorship	The Inst. of Electr. and Electron. Eng. The IEEE Signal Processing Soc. The IEEE Circuits and Syst. Soc
Starting Page	321
Ending Page	324
File Size	328158
Page Count	4
File Format	PDF
ISBN	0780385047
DOI	10.1109/SIPS.2004.1363070
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2004-10-13
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Finite impulse response filter Optimization methods Attenuation Digital filters Field programmable gate arrays Batteries 3G mobile communication Energy consumption Circuit synthesis Telephony
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

Xilinx Virtex II Pro implementation of a reconfigurable UMTS digital channel filter

Adaptive FIR filter architectures for run-time reconfigurable FPGAs

Low-power reconfigurable VLSI architecture for the implementation of FIR filters

Digital FIR Filter Optimization Using Toggle-Based Power Estimation Tools

The implementation methods of high speed FIR filter on FPGA

Efficient FPGA and ASIC Realizations of a DA-Based Reconfigurable FIR Digital Filter

ASIC implementation architecture for pulse shaping FIR filters in 3G mobile communications

Low-power FIR filter design on FPGAs

A dynamic partial reconfigurable FIR filter architecture

Power optimization of a reconfigurable FIR-filter

Similar Documents

Xilinx Virtex II Pro implementation of a reconfigurable UMTS digital channel filter

Adaptive FIR filter architectures for run-time reconfigurable FPGAs

Low-power reconfigurable VLSI architecture for the implementation of FIR filters

Digital FIR Filter Optimization Using Toggle-Based Power Estimation Tools

The implementation methods of high speed FIR filter on FPGA

Efficient FPGA and ASIC Realizations of a DA-Based Reconfigurable FIR Digital Filter

ASIC implementation architecture for pulse shaping FIR filters in 3G mobile communications

Low-power FIR filter design on FPGAs

A dynamic partial reconfigurable FIR filter architecture

Power optimization of a reconfigurable FIR-filter