NDLI: Novel low power pipelined FFT based on subexpression sharing for wireless LAN applications

Content Provider	IEEE Xplore Digital Library
Author	Wei Han Arslan, T. Erdogan, A.T. Hasan, M.
Copyright Year	2004
Description	Author affiliation: Sch. of Eng. & Electron., Edinburgh Univ., UK (Wei Han; Arslan, T.; Erdogan, A.T.; Hasan, M.)
Abstract	This paper proposes a novel low power multiplierless radix-4 single-path delay commutator (R4SDC) FFT processor architecture for wireless LAN (IEEE 802.11 standard) applications, where short FFT are utilised in the implementation of the physical layer. The multiplierless architecture uses shift and addition operations to realize complex multiplications. By combining a new commutator architecture, and low power butterfly architectures with this approach, the resulting power savings are around 19% and 35% for 64-point and 16-point radix-4 FFT respectively, as compared to a conventional FFT architecture based on non-Booth coded Wallace tree multiplier.
Sponsorship	The Inst. of Electr. and Electron. Eng. The IEEE Signal Processing Soc. The IEEE Circuits and Syst. Soc
Starting Page	83
Ending Page	88
File Size	371758
Page Count	6
File Format	PDF
ISBN	0780385047
DOI	10.1109/SIPS.2004.1363029
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2004-10-13
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Wireless LAN Flexible printed circuits Energy consumption Discrete Fourier transforms OFDM Digital video broadcasting Equations Power engineering and energy Delay Physical layer
Content Type	Text
Resource Type	Article

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