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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Wolfs, P. Thomas, P. |
| Copyright Year | 2007 |
| Description | Author affiliation: Central Queensland Univ., Rockhampton (Wolfs, P.; Thomas, P.) |
| Abstract | The time domain step response for rapid load changes can be improved in boost type power factor correction circuits by using a capacitor voltage model. In single phase PFC circuits, the dc bus voltage must have a significant voltage ripple at twice the mains frequency due to energy balance requirements. In traditional implementations, the presence of this ripple voltage causes a trade-off between line current wave shape and speed of the dc output regulatory response. The capacitor voltage model provides a ripple free estimate of the storage capacitor voltage. This allows the bandwidth of the dc bus voltage regulation loop to increase without causing a degradation of line current wave shape. Simulations show that the dc regulatory response is complete within one mains cycle and significant reductions in voltage over and under-shoots are achieved. |
| Starting Page | 1314 |
| Ending Page | 1318 |
| File Size | 560057 |
| Page Count | 5 |
| File Format | |
| ISBN | 9781424406548 |
| ISSN | 02759306 |
| DOI | 10.1109/PESC.2007.4342184 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2007-06-17 |
| Publisher Place | USA |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Rectifiers Power factor correction Circuits Power system harmonics Voltage control Capacitors Shape Frequency Bandwidth Degradation model referenced control boost rectifier |
| Content Type | Text |
| Resource Type | Article |
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