NDLI: Design of a VLSI processor chip for three-dimensional instrumentation

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Design of a VLSI processor chip for three-dimensional instrumentation

Content Provider	IEEE Xplore Digital Library
Author	Seunghwan Lee Hariyama, M. Kameyama, M.
Copyright Year	1997
Description	Author affiliation: Dept. of Comput. & Math. Sci., Tohoku Univ., Sendai, Japan (Seunghwan Lee)
Abstract	Three-dimensional (3-D) instrumentation based on optical flow is a promising instrumentation method for intelligent systems in which accurate 3-D information is required. However, real-time instrumentation is difficult since much computation time and a large memory bandwidth are required. In this paper, a 3D instrumentation VLSI processor with a concurrent memory-access scheme is proposed. To reduce the access time, frequently used data are stored in a cache register array and are concurrently transferred to processing elements using simple interconnections to the 8 nearest neighbor registers. Based on a row and column memory access pattern, we propose a diagonally interleaved frame memory by which pixel values of a row and column are stored across memory modules. Therefore, the pixel values are read in parallel from the frame memory. Based on the concurrent memory-access scheme, the performance of the processor is 2 million times faster than that of a 28.5 MIPS workstation.
Starting Page	951
Ending Page	954
File Size	356422
Page Count	4
File Format	PDF
DOI	10.1109/SICE.1997.624886
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1997-07-29
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Very large scale integration Instruments Registers Image sequences Intelligent systems Workstations Intelligent robots Intelligent vehicles Pixel Robot kinematics
Content Type	Text
Resource Type	Article

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