NDLI: High performance air-cooled temperature margining thermal tools for silicon validation

Content Provider	IEEE Xplore Digital Library
Author	Mohammed, R. Sahan, R. Yi Xia Ying-feng Pang
Copyright Year	2011
Description	Author affiliation: Platform Validation Engineering, Intel Corporation, 3600 Juliette Lane, MS SC12-214, Santa Clara, CA 95054 (Mohammed, R.; Sahan, R.; Yi Xia; Ying-feng Pang)
Abstract	Thermal tools provide temperature margining capability by varying the case temperature at silicon thermal design power (TDP). They are used for process, voltage, temperature and frequency (PVTF) testing by Intel's post-silicon validation customers across servers, desktops, mobile and graphics segments. Thermal margining tools are widely used in silicon debug validation by varying the case temperature over a wide operating range of specifications of the Silicon to i) validate the silicon, ii) accelerate fault detection, and iii) reduce escapes and identify bugs. Thermal tool is controlled by a thermal controller to provide a temperature set-point based on the device under test's (DUT's) case or junction diode temperature. Air cooled thermal tool (AC-TT) employs a controller card to achieve the margining capability by running the tool's thermoelectric cooler (TEC), a Peltier device, within the optimal temperature range. AC-TT has an active heat sink design to remove the heat dissipated by the TEC and the silicon. Although AC-TT is expected to provide narrower range of margining capability due to the limitations of air cooling, they still can be an excellent solution for some specific thermal margining applications. Therefore, a new line of AC-TTs were developed for validation customers whose needs can be addressed without requiring costly controllers and noisy chillers while enhancing the user-experience. This paper presents the design improvement strategies implemented for developing the new line of CPU, Chipset and ASIC AC-TTs. Improved designs provide wider margining capability by using i) high performance active heat sink designs, ii) high power thermo-electric cooler (TEC), iii) cold plate designs compatible to keep out volume (KOV), iv) new choice of thermal interface material (TIM), and v) new retention design. This paper discusses the details of the design process and how multiple design strategies are implemented to finalize the design and to achieve the overall performance improvement while keeping the cost of the AC-TT low. The new line of AC-TT designs have performance improvement of 44% (∼25C) for 130W CPU TT compared to existing CPU AC-TT, of 32% (∼19C) for 60W chipset compared to existing chipset AC-TT, and of 41% (∼8C) compared to existing 15W PCH (Peripheral Component Hub) AC-TT. Design strategies provided here can be easily adapted to develop future generation of low-cost CPU, chipset, and ASIC AC-TTs with a wider margining capability.
Starting Page	265
Ending Page	271
File Size	697225
Page Count	7
File Format	PDF
ISBN	9781612847405
ISSN	10652221
e-ISBN	9781612847368
DOI	10.1109/STHERM.2011.5767210
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2011-03-20
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Heat sinks Silicon Cold plates Heating Heat transfer Thermal resistance temperature margining Thermal tool CPU chipset ASIC retention design CFD TEC air cooling TIM
Content Type	Text
Resource Type	Article

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