NDLI: Optimize WIP scale through simulation approach with WIP, turn-over rate and cycle time regression analysis in semiconductor fabrication

Content Provider	IEEE Xplore Digital Library
Author	Wei Jie Lee
Copyright Year	2002
Description	Author affiliation: UMC, Hsinchu, Taiwan (Wei Jie Lee)
Abstract	In a foundry semiconductor fabrication the goal of achieving maximum profits is maximizing the wafer out target on a premise of acceptable cycle time. This paper presents and applies a methodology for determining the optimal WIP scale of an IC manufacturing fab. From the simulation result obtained, we experimentally confirmed that there is a positive correlation between WIP and Cycle Time, negative correlation between WIP and turn-over rate. Further, we built a second-order regression model for WIP and wafer out correlation, and obtained an absolute maximum wafer out volume based on an acceptable WIP level.
Sponsorship	Taiwan Semicond. Ind. Assoc. (TSIA) IEEE Electron Devices Soc. Taipei Chapter IEEE Electron Devices Soc. Committee for Precision Machinery Ind. Dev. MOEA Semicond. Ind. Promotion Office Ind. Dev. Bureau, MOEA
Starting Page	299
Ending Page	301
File Size	155570
Page Count	3
File Format	PDF
ISBN	0780376048
DOI	10.1109/SMTW.2002.1197452
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2002-12-11
Publisher Place	China
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Analytical models Regression analysis Fabrication Semiconductor device modeling Semiconductor process modeling Predictive models Discrete event simulation Foundries Production facilities Cities and towns
Content Type	Text
Resource Type	Article

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