NDLI: Pseudo Epi, materials cost reduction

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2001 IEEE International Symposium on Semiconductor Manufacturing. ISSM 2001. Conference Proceedings (Cat. No.01CH37203)

2001 IEEE International Symposium on Semiconductor Manufacturing. ISSM 2001. Conference Proceedings (Cat. No.01CH37203)

A comparison of unified vs. segregated automated material handling systems for 300 mm fabs

Agile fab concepts for cost effective and QTAT mini fab

Cleanroom design for Cu-CMP processes

Interoperable communication specification for AMHS

Unified tool communication specification for 300 mm automated fab

Managing, measuring and improving equipment capacity and overall equipment efficiency (OEE) using iPLUS

TekPAC (Technical Electronic Knowledge Personal Assistant Capsule)

Optimization and economic analysis for tool portfolio planning in semiconductor manufacturing

The economic impact of choosing off-line, inline or in situ metrology deployment in semiconductor manufacturing

B2B in TSMC turnkey services [semiconductor manufacturing]

The development of security system and visual service support software for on-line diagnostics

Wafer level tracking and control to full mini-environment line

Universal architecture to improve equipment maintenance work

A new manufacturing control system using Mahalanobis distance for maximising productivity

Using real time dispatcher as a decision-making support system to resolve overlapping dispatching problem in FAB manufacturing

Comprehensive cost-effective photo defect monitoring strategy

Dynamic simulator for WIP analysis in semiconductor manufacturing

Optimal etch time control design using neuro-dynamic programming

Simple tool of analysis for cycle time reduction

Dynamical control method of AMHS for multi-production lines

Two approaches to determine appropriated fab manufacturing production plan by cycle-time and WIP energy

Material management system with the function of estimated number based on production control system

Comprehensive cycle time reduction program at AMD's fab25

An automatic monitor management system for effective 300 mm fab operations

Talking shop - linking training to factory indicators

Reconciling high-speed scheduling with dispatching in wafer fabs

Lithography-less ion implantation technology for agile fab

Novel pulse pressure CVD for void free STI trench TEOS fill

Wafer ambient control for Agile FAB

Improvement of CD uniformity in 180 nm LSI manufacturing by optimizing illumination system

Phi-scatterometry for integrated linewidth control in DRAM manufacturing

Full profile inter-layer dielectric CMP analysis

Towards a complete plasma diagnostic system

Spectroscopic CD technology for gate process control

Multi-wafer rapid isothermal processing

Plasma charging defect inspection and monitors in poly-buffered STI

Development of a two-step electroplating process with a long-term stability for applying to Cu metallization of 0.1 /spl mu/m generation logic ULSIs

Control of FSG/SiO/sub 2/ interlayer conditions to prevent Al-wiring delamination caused by F accumulation at Ti/SiO/sub 2/

Characterization of metallic impurities for the ULSI fabrication process

Pseudo Epi, materials cost reduction

Data mining and fault diagnosis based on wafer acceptance test data and in-line manufacturing data

Suppression of MOSFET reverse short channel effect by channel doping through gate electrode

Base oxide scaling limit of thermally-enhanced remote plasma nitridation (TE-RPN) process for ultra-thin gate dielectric formation

Control of edge polishing profile with air float carrier

Scaling challenges for 0.13 /spl mu/m generation shallow trench isolation

Microeconomics of accelerated shrinks in demand-limited markets

Shallow trench isolation scatterometry metrology in a high volume fab

Photoresist stripping using novel sulfuric/ozone process

Low k material optimization

Multiple objective APC application for an oxide CMP process in a high volume production environment

Low cost and high reliability CMOS technologies, by "retro process sequence"

Benchmarking 193 nm photoresists for etch resistance

An environmentally friendly photoresist and ashing residue remover for Cu/low-k devices

Resource conservation of buffered HF in semiconductor manufacturing

Reduction of PFC emissions by gas circulation cleaning in plasma CVD

Development of photo-resist stripping process using ozone and water vapor

Highly sensitive inspection system for lithography-related faults in agile-fab detecting algorithm, monitoring and evaluation of yield impact

A plausible model and solutions for an HSQ-related volume shrinkage of aluminum landing pad

New method of extraction of systematic failure component

Nanoscale fault isolation technique by conducting atomic force microscopy

Yield improvement by avoiding a metal chemical reaction in the metal etching post-treatment

Novel strategies of FSG-CMP for within-wafer uniformity improvement and wafer edge yield enhancement beyond 0.18 micro technologies

Layout manufacturability analysis using rigorous 3-d topography simulation

Yield improvement through cycle time and process fluctuation analyses

Acceleration of yield enhancement activity by utilizing real-time fail bitmap analysis

Characterization algorithm of failure distribution for LSI yield improvement

A non-traditional approach to resolving multi-layer process-induced metal voiding

Methodology for yield analysis based on targeted defect impact studies

Silicide-related yield enhancement in a deep submicrometer CMOS process

Study of high density plasma etch for borderless contact to solve bottom anti-reflective coating defect for beyond 0.18 /spl mu/m VLSI technology

Bond pad F-crystal defect control and monitoring

Cleaning technique of hot-wall batch type Ru CVD equipment by oxygen gas

Emitter polysilicon process optimization by RGA and process proposal for interfacial oxide growth using ozonated water

Methods of stabilizing linewidths in photolithography for improving ASIC plant productivity

Polymer control in aluminum etch chambers to achieve >450 hours MTBC

A study on ILD process of simple and CMP skip using polysilazane-based SOG

CMP defect reduction by micro-scratch control using new monitoring technique

Advanced EB-cure process and equipment for low-k dielectric

Suppression of micro-bubbles in photoresist coating by step dynamic coating

Controlling Ru airborne contamination in cleanroom

Novel retaining ring to reduce CMP edge exclusion

Defect management technology for 100 nm generation

A laser formed MakeLink* for customization and repair

An integrated engineering approach to improve wafer edge yield

Nano-scale defect investigation by site-specific transmission electron microscopy and electron energy loss spectroscopy

Characteristics of UV confocal microscopy inspection for detecting 0.1 /spl mu/m level defects

A novel pad conditioning disk design of tungsten chemical mechanical polishing process for deep sub-micron device yield improvement

Comparative analysis of 300 mm FAB architectures impact of equipment sets on wafer cost and dynamic performance

Evaluation of advantages of integrating 300 mm AMHS fab layouts in the photo area

300 mm factory automation experience and challenges for wafer foundry fabs

Floor layout planning method based on self-organization

Capacity calculation of an AGV system in a MP2 wafer fab by means of simulation

In-situ CMP copper endpoint control system

Gate stack preparation with high-k materials in a cluster tool

Development of automated contact inspection system using in-line CD SEM

Optimum drying method for scan coating

Interferometric techniques for dielectric trench etch applications

Cycle time advantages of mini batch manufacturing and integrated metrology in a 300 mm vertical furnace

Development of the inspection system of defects on a CMP (Chemical Mechanical Polishing) pad

The practical use of residual gas analysis in a semiconductor thermal processing module

Managing and controlling contamination in an advanced 8" CMOS pilot line

Simulation and dispatching systems for production fab management

The QUEST System in Intel Fab18: a web-based method for the management of quality

The impact of e-diagnostics - one year later

Development of data logging system for chemical mechanical polishing and its application for process control

Gas cleaning technique for batch furnace at Agile-fab concept manufacturing

Remote equipment diagnosis for metal etching process

Novel approach for precise control of oxide thickness

Concurrent fault tolerant control of semiconductor measurement and testing

Throughput improvement in photolithography processing for flexible production

Low cost and compact solution for recycling PFCs by the continuous gas chromatography

High-sensitive organic contaminants detecting method based on cold-trap and multiple-internal-reflection FTIR [clean room air monitoring systems]

A fact-finding survey on the heat generation from processing equipment at a semiconductor fab under operation

Energy saving in semiconductor fabs by using vacuum insulator

Photoresist developer reclamation technology and system

New chemical removing and air cooling technology for clean room recirculation air using chilled pure water showering method

FOUP cleaning - FOSB transportation: a challenge for manufacturing on 300 mm wafers

Development of the next generation Si wafer transfer/stock system

Pre-metal clean optimization for cluster defect prevention

Improvement of 300mm FOUP mini-environment

Development and implementation of a sustainable operator training and certification process

Labor modeling in a dynamic environment

ISSM 2001 index of presenters

Proceedings of ISSM2000. Ninth International Symposium on Semiconductor Manufacturing (IEEE Cat. No.00CH37130)

1999 IEEE International Symposium on Semiconductor Manufacturing Conference Proceedings (Cat No.99CH36314)

1997 IEEE International Symposium on Semiconductor Manufacturing Conference Proceedings (Cat. No.97CH36023)

Proceedings of International Symposium on Semiconductor Manufacturing

International Symposium on Semiconductor Manufacturing, Extended Abstracts of ISSM

International Symposium on Semiconductor Manufacturing

Pseudo Epi, materials cost reduction

Content Provider	IEEE Xplore Digital Library
Author	Aminzadeh, M. Ravi, K.V. Sery, G. Hu, S.
Copyright Year	2001
Description	Author affiliation: Intel Corp., Santa Clara, CA, USA (Aminzadeh, M.)
Abstract	Historically Intel has used p/p+ epitaxial wafers for all products for more than 15 years. The epitaxial wafers have several key characteristics such as latch up immunity, oxygen free active area, and superior oxide quality compared to polished non-epi wafers. The epi wafers however are large materials cost contributors. Pseudo epi is an alternative to epi wafers with equivalent device performance and material cost savings of 25 to 30%. Pseudo epi or hydrogen anneal is expected to save Intel 6% of total 200 mm Si production costs in 2002 for one chipset process line. This savings is expected to increase to equivalent of 13% of 200 mm Si production cost when expanded to a 0.13 /spl mu/m microprocessor process.
Sponsorship	IEEE Electron Devices Soc.
Starting Page	167
Ending Page	170
File Size	487845
Page Count	4
File Format	PDF
ISBN	0780367316
DOI	10.1109/ISSM.2001.962940
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2001-10-08
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Costs Gettering Annealing Silicon Hydrogen Boron Temperature Production Rough surfaces Surface roughness
Content Type	Text
Resource Type	Article

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