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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Frank, G. Hartmann, G. |
| Copyright Year | 1995 |
| Description | Author affiliation: Dept. of Electr. & Electron. Eng., Paderborn Univ., Germany (Frank, G.; Hartmann, G.) |
| Abstract | The following report introduces the hardware design of a neuro-computer aligned to simulate large neural nets consisting of pulse-coded model neurons. The simulation process is carried out in real-time, referring to image processing. A single accelerator provides 32k neurons with 128 synapses each. There is no need to assign a fixed number of synaptic weights to each neuron rather then distributing the total amount of four million synapses arbitrary to any neuron. The simulation of larger nets is possible by connecting the accelerators in a hexagonal structure, where the simulation time will only increase if the overall activity of the net mainly effects one specific accelerator board. |
| Starting Page | 2014 |
| Ending Page | 2018 |
| File Size | 508715 |
| Page Count | 5 |
| File Format | |
| ISBN | 0780327683 |
| DOI | 10.1109/ICNN.1995.488982 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 1995-11-27 |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Artificial neural networks Neurons Hardware Biological system modeling Joining processes Computational modeling Visual system Electron accelerators Humans Object recognition |
| Content Type | Text |
| Resource Type | Article |
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