NDLI: A recurrent neural network with serial delay elements for memorizing limit cycles

Content Provider	IEEE Xplore Digital Library
Author	Miyoshi, S. Nakayama, K.
Copyright Year	1995
Description	Author affiliation: Graduate Sch. of Natural Sci. & Technol., Kanazawa Univ., Japan (Miyoshi, S.)
Abstract	A recurrent neural network (RNN), in which each unit has serial delay elements, is proposed for memorizing limit cycles (LCs). This network is called DRNN in this paper. An LC consists of several basic patterns. The hysteresis information of LCs, realized on the connections from the delay elements to the units, is very efficient in the following reasons. First, the same basic patterns can be shared by different LCs. This make it possible to drastically increase the number of LCs, even though using a small number of the basic patterns. Second, noise performance, that is, probability of recalling the exact LC starting from the noisy LC, can be improved. The hysteresis information consists of two components, the order of the basic patterns included in an LC, and the cross-correlation among all the basic patterns. The former is highly dependent on the number of LCs, and the latter the number of all the basic patterns. In order to achieve good noise performance, a small number of the basic patterns is preferred. These properties of the DRNN are theoretically analyzed and confirmed through computer simulations. It is also confirmed that the DRNN is superior to the RNN without delay elements for memorizing LCs.
Starting Page	1955
Ending Page	1960
File Size	531856
Page Count	6
File Format	PDF
ISBN	0780327683
DOI	10.1109/ICNN.1995.488970
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1995-11-27
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Recurrent neural networks Limit-cycles Hysteresis Computer simulation Artificial neural networks Error correction Associative memory Delay effects Discrete time systems Pattern analysis
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in