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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Al-Sanie, K.M. |
| Copyright Year | 1995 |
| Description | Author affiliation: Dept. of Electr. Eng., King Saud Univ., Riyadh, Saudi Arabia (Al-Sanie, K.M.) |
| Abstract | In this paper, we present a new type-II hybrid ARQ scheme. This scheme employs block coded modulation (BCM) for error-correction and a linear block code for error-defection. This scheme is referred to as the BCM-ARQ scheme. Rate 1/2 block code with QPSK as error-correction code is considered. Computer simulation is used to evaluate the throughout of the proposed scheme. In comparison with the classical ARQ schemes, the proposed ARQ scheme provides enhanced throughout under high probability of error conditions without any increase in the bandwidth. A BCM-ARQ scheme with combining of successive received blocks is also introduced. In this scheme, the decoder for error correction operates on a combination of all received sequences for a block rather than only on the most recent received one. It is shown that blocks combining further improves the throughput of the BCM-ARQ scheme for higher channel error rate. |
| Starting Page | 463 |
| Ending Page | 467 |
| File Size | 432743 |
| Page Count | 5 |
| File Format | |
| ISBN | 0780325796 |
| DOI | 10.1109/SICON.1995.526330 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 1995-07-03 |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Automatic repeat request Modulation coding Computer errors Block codes Quadrature phase shift keying Error correction codes Computer simulation Bandwidth Decoding Error correction |
| Content Type | Text |
| Resource Type | Article |
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