NDLI: On Practical Multiplexing Issues

Content Provider	IEEE Xplore Digital Library
Author	Beiu, V. Sulieman, M.H.
Copyright Year	2006
Description	Author affiliation: College of Information Technology, United Arab Emirates University, Al Ain, United Arab Emirates, vbeiu@uaeu.ac.ae (Beiu, V.)
Abstract	This paper investigates the behavior of multiplexing schemes in combination with elementary gates. The two schemes under investigation are MAJORITY- and NAND-multiplexing. The simulation results are for single-electron technology (SET), where the elementary components of the gates (capacitors in the case of capacitive-SET) are subjected to geometric variations. First, the elementary gates are compared in terms of their intrinsic probability of failure with respect to variations. Secondly, the two multiplexing schemes are weighted against the reliability enhancements they are able to bring into the system. This study gives insights into the behavior of fault-tolerant multiplexing schemes and shows how the logic styles, as well as the technology, could affect the overall reliability of a multiplexed system. Such aspects should be carefully weighted for the design of future nano-architectures.
Starting Page	310
Ending Page	313
File Size	213142
Page Count	4
File Format	PDF
ISBN	1424400775
DOI	10.1109/NANO.2006.247637
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2006-07-17
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Redundancy CMOS technology Nanoscale devices Capacitors Electrons Uncertainty Power dissipation Educational institutions Information technology Solid modeling single electron technology (SET) Fault-tolerance multiplexing reliability
Content Type	Text
Resource Type	Article

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