NDLI: Synthesis of Reversible Circuits with No Ancilla Bits for Large Reversible Functions Specified with Bit Equations

Content Provider	IEEE Xplore Digital Library
Author	Alhagi, N. Hawash, M. Perkowski, M.
Copyright Year	2010
Abstract	This paper presents a new algorithm MP(multiple pass) to synthesize large reversible binary circuits without ancilla bits. The MMD algorithm requires to store a truth table (or a Reed-Muller -RM transform) as a 2^n vector for a reversible function of n variables. This representation prohibits synthesis of large functions. However, in MP we do not store such an exponentially growing data structure. The values of minterms are calculated in MP dynamically, one-by-one, from a set of logic equations that specify the reversible circuit to be designed. This allows for synthesis of large scale reversible circuits (30-bits), which is not possible with existing algorithms. In addition, our unique multipass approach where the circuit is synthesized with various, yet specific, minterm orders yields optimal solution. The algorithm returns a description of the optimal circuit with respect to gate count or quantum cost. Although the synthesis process is relatively slower, the solution is found in real-time for smaller circuits of 8 bits or less
Starting Page	39
Ending Page	45
File Size	387195
Page Count	7
File Format	PDF
ISBN	9781424467525
ISSN	0195623X
e-ISBN	9781424467532
DOI	10.1109/ISMVL.2010.16
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2010-05-26
Publisher Place	Spain
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Circuit synthesis Equations Convergence Logic circuits Cost function Transforms Data structures Logic design Large-scale systems Synthesizers ancilla bit MMD MMDS MMDSN Large Reversible Circuits Logic Synthesis 30-bit Hasse diagram line blocking
Content Type	Text
Resource Type	Article
Subject	Mathematics Computer Science

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