NDLI: Scalable Architectures for Design of Reversible Quaternary Multiplexer and Demultiplexer Circuits

Content Provider	IEEE Xplore Digital Library
Author	Khan, M.H.A.
Copyright Year	2009
Abstract	Quaternary reversible logic is very suitable for encoded realization of binary reversible logic functions by grouping two bits together into quaternary digits. Quaternary multiplexer and demultiplexer circuits are very important building blocks of quaternary digital systems. In this paper, we show reversible realizations of 4x1 multiplexer and 1x4 demultiplexer circuits on the top of liquid ion-trap realizable 1x1 and Muthukrishnan-Stroud gates. Then we show scalable architectures for design of mx1 multiplexer and 1xm demultiplexer circuits using 4x1 multiplexers and 1x4 demultiplexers, respectively, where m ≤ 4n and n is the number of selection inputs. The proposed realizations of reversible multiplexer and demultiplexer circuits are more efficient than the earlier realizations in terms of number of primitive gates and number of ancilla inputs required.
Starting Page	343
Ending Page	348
File Size	251426
Page Count	6
File Format	PDF
ISBN	9781424438419
ISSN	0195623X
DOI	10.1109/ISMVL.2009.26
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2009-05-21
Publisher Place	Japan
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Multiplexing Logic functions Digital systems Circuit synthesis Galois fields Arithmetic Logic gates Logic design Logic circuits Computer architecture Quaternary Logic Multiplexer Demultiplexer Reversible Logic
Content Type	Text
Resource Type	Article
Subject	Mathematics Computer Science

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