NDLI: 16-level Current-Mode Multiple-Valued Dynamic Memory with Increased Noise Margin

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2015 IEEE International Symposium on Multiple-Valued Logic

2014 IEEE 44th International Symposium on Multiple-Valued Logic

2013 IEEE 43rd International Symposium on Multiple-Valued Logic

2012 IEEE 42nd International Symposium on Multiple-Valued Logic

2011 41st IEEE International Symposium on Multiple-Valued Logic

2010 40th IEEE International Symposium on Multiple-Valued Logic

2009 39th International Symposium on Multiple-Valued Logic

Table of Contents

Message from the Symposium Chair

Message from the Program Chair

Symposium Committees

Counting Problems and Clones of Functions

Web-Based Nursing Care Quality Improvement System with Fuzzy Recommendation System

A Study of Practical Causality Acquisition among Vital Signals

Biometric System by Foot Pressure Change Based on Neural Network

Fuzzy Logic Assisted Quantification of Gyral Deformation Index Using Magnetic Resonance Images for the Infantile Brain

Fuzzy Rule Extraction from Nursing-Care Texts

Robust Multiple-Valued Current-Mode Circuit Components Based on Adaptive Reference-Voltage Control

Optimization of Current-Mode MVD-ORNS Arithmetic Circuits

16-level Current-Mode Multiple-Valued Dynamic Memory with Increased Noise Margin

Multiple-Valued Reconfigurable VLSI Processor Based on Superposition of Data and Control Signals

Timing-Variation-Aware Multiple-Valued Current-Mode Circuit for a Low-Power Pipelined System

Mining Approximative Descriptions of Sets Using Rough Sets

Positive Primitive Structures

Paradigms for Non-classical Substitutions

Bounding the Phase Transition on Edge Matching Puzzles

Efficient Implementation of Controlled Operations for Multivalued Quantum Logic

Quantum Finite State Machines as Sequential Quantum Circuits

Synthesis of GF(3) Based Reversible/Quantum Logic Circuits without Garbage Output

Quantum Realization of Multiple-Valued Feynman and Toffoli Gates without Ancilla Input

Multi-valued Modal Fixed Point Logics for Model Checking

Minimal Coverings of Maximal Partial Clones

Frozen Boolean Partial Co-clones

The Minimal Covering of Maximal Partial Clones in 4-valued Logic

On the Guidance of Reversible Logic Synthesis by Dynamic Variable Reordering

Design of a High-Speed Fuzzy Logic Controller Based on Log-Domain Arithmetic

The Use of Multiple Connected Pseudo Minterms in the Synthesis of MVL Functions

A Two-Pronged Approach of Power-Aware Voltage Scheduling for Real-Time Task Graphs in Multi-processor Systems

Computational Neuroscience and Multiple-Valued Logic

Hyperclones Determined by Total-Parts of Hyper-relations

On Endoprimal Monoids in Clone Theory

Partial Clones Containing All Selfdual Monotonic Boolean Partial Functions

On Periodic Patterns and their Spectra

Generalized Discrete Hartley Transforms

Generating Hard Instances for MaxSAT

Regular Encodings from Max-CSP into Partial Max-SAT

Multi-level Signaling for Chip-to-Chip and Backplane Communication (A Tutorial)

An Overview of a Software Tool in Rough Non-deterministic Information Analysis

On Decision Making under Interval Uncertainty: A New Justification of Hurwicz Optimism-Pessimism Approach and its Use in Group Decision Making

Optimization of Fuzzy If-Then Rule Bases by Evolutionary Tuning of the Operations

Non-convex Fuzzy Truth Values and De Morgan Bisemilattices

Evaluation of the Hierarchical Temporal Memory as Soft Computing Platform and its VLSI Architecture

Multiple-Valued Constant-Power Adder for Cryptographic Processors

Time-Interleaved Polyphase Decimation Filter Using Signed-Digit Adders

Multiple-Valued Data Transmission Based on Time-Domain Pre-emphasis Techniques in Consideration of Higher-Order Channel Effects

Quaternary Addition Circuits Based on SUSLOC Voltage-Mode Cells and Modeling with SystemVerilog©

Multiple Valued Logic Algebra for the Synthesis of Digital Circuits

Designing and Using FPGAs beyond Classical Binary Logic: Opportunities in Nano-Scale Integration Age

Attribute Reduction as Calculation of Focus in Granular Reasoning

Clarifying the Systems of Axioms Based on the Method of Indeterminate Coefficients

Applying Rough Sets to Information Tables Containing Missing Values

Generalized Extended t-Norms as t-Norms of Type 2

Evaluation of Cardinality Constraints on SMT-Based Debugging

Application of Covering Codes for Reduced Representations of Logic Functions

Ternary Logic by 3rd Subharmonics and its Application to Multiway Switches

Fixed Polarity Quaternary Transforms Derived from Linearly Independent Transform over GF(2) Structure

Equivalence Checking of Reversible Circuits

Multi-path Switching Device Utilizing a Multi-terminal Nanowire Junction for MDD-Based Logic Circuit

Multiple-Valued Logic Gates Using Asymmetric Single-Electron Transistors

Scalable Architectures for Design of Reversible Quaternary Multiplexer and Demultiplexer Circuits

Floating-Point Numerical Function Generators Using EVMDDs for Monotone Elementary Functions

Representing the Genetic Code as a Function on a Galois Field Using the Reed-Muller Expansion

A Quaternary Decision Diagram Machine and the Optimization of its Code

Quaternary Reed-Muller Expansions of Mixed Radix Arguments in Cryptographic Circuits

38th International Symposium on Multiple Valued Logic (ismvl 2008)

37th International Symposium on Multiple-Valued Logic (ISMVL'07)

36th International Symposium on Multiple-Valued Logic (ISMVL'06)

35th International Symposium on Multiple-Valued Logic (ISMVL'05)

Proceedings. 34th International Symposium on Multiple-Valued Logic

33rd International Symposium on Multiple-Valued Logic, 2003. Proceedings.

Proceedings 32nd IEEE International Symposium on Multiple-Valued Logic

Proceedings 31st IEEE International Symposium on Multiple-Valued Logic

Proceedings 30th IEEE International Symposium on Multiple-Valued Logic (ISMVL 2000)

Proceedings 1999 29th IEEE International Symposium on Multiple-Valued Logic (Cat. No.99CB36329)

Proceedings. 1998 28th IEEE International Symposium on Multiple- Valued Logic (Cat. No.98CB36138)

Proceedings 1997 27th International Symposium on Multiple- Valued Logic

Proceedings of 26th IEEE International Symposium on Multiple-Valued Logic (ISMVL'96)

Proceedings 25th International Symposium on Multiple-Valued Logic

Proceedings of 24th International Symposium on Multiple-Valued Logic (ISMVL'94)

[1993] Proceedings of the Twenty-Third International Symposium on Multiple-Valued Logic

[1992] Proceedings The Twenty-Second International Symposium on Multiple-Valued Logic

[1991] Proceedings of the Twenty-First International Symposium on Multiple-Valued Logic

Proceedings of the Twentieth International Symposium on Multiple-Valued Logic

Proceedings. The Nineteenth International Symposium on Multiple-Valued Logic

[1988] Proceedings. The Eighteenth International Symposium on Multiple-Valued Logic

16-level Current-Mode Multiple-Valued Dynamic Memory with Increased Noise Margin

Content Provider	IEEE Xplore Digital Library
Author	Khodabndehloo, G. Mirhassani, M. Ahmadi, M.
Copyright Year	2009
Abstract	Design and implementation of a novel 16-level multiple-valued memory is proposed. Each memory cell uses equivalent to one binary digit to detect the error due to leakage currents. Moreover, this feature increases the noise margin of the system by a factor of two. The refreshing circuitry is based on a series configuration of A/D and D/A converters for each data line. The error correction and storage scheme is based on a recently developed Multiple-Valued representation, calledContinuous Valued Number System (CVNS). This memory cell can be used in hardware implementation of multiple-valued neural networks based on the CVNS.
Starting Page	48
Ending Page	53
File Size	643569
Page Count	6
File Format	PDF
ISBN	9781424438419
ISSN	0195623X
DOI	10.1109/ISMVL.2009.12
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2009-05-21
Publisher Place	Japan
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Random access memory Voltage Capacitors Neural networks Arithmetic Redundancy Leakage current Circuits Logic Leak detection noise margin multiple-valued memory CVNS error correction
Content Type	Text
Resource Type	Article
Subject	Mathematics Computer Science

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