NDLI: An efficient pipelined fast and multiplier-less 2-D IDCT for image/video decoding

Content Provider	IEEE Xplore Digital Library
Author	El Aakif, M. Belkouch, S. Hassani, M.M.
Copyright Year	2011
Description	Author affiliation: Embedded Systems and Digital Control Laboratory, National School of Applied Sciences, University of Cadi, Ayyad, PB. 575, Av. Abdelkarim Khattabi, Guéliz, Marrakech, Morocco (El Aakif, M.; Belkouch, S.) \|\| Electronics and Instrumentation Laboratory, Faculty of Sciences Semlalia, University of Cadi Ayyad, Marrakech, Morocco (Hassani, M.M.)
Abstract	In this paper, an efficient pipelined fast and multiplier-Less 2-D IDCT (Inverse Discrete Cosine Transform) is performed with a new FGA (Flow-Graph Algorithm) of 1-D IDCT based on Loeffler algorithm. Two other 2-D IDCT architectures are performed in order to compare their FGAs based on Loeffler with the proposed one in term of the frequency operation and the resources usage. The multiplier-less method is used with optimization to avoid the multiplications which is replaced by a minimum number of additions and shifts. Optimizations of the critical paths brought by the proposed FGA are presented. The results show the increase of the maximum frequency and the decrease of the resources usage with a new proposed FGA algorithm.
Starting Page	1
Ending Page	5
File Size	456005
Page Count	5
File Format	PDF
ISBN	9781612847306
e-ISBN	9781612847320
DOI	10.1109/ICMCS.2011.5945687
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2011-04-07
Publisher Place	Morocco
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Discrete cosine transforms Computer architecture Hardware Algorithm design and analysis Decoding Optimization Equations Decompression 2-D IDCT 1-D IDCT Flow Graph Algorithm Multiplier-Less FPGA
Content Type	Text
Resource Type	Article

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