NDLI: Area and Memory Efficient Architectures for 3D Blu-ray-compliant Multimedia Processors

Content Provider	IEEE Xplore Digital Library
Author	Chi-Cheng Ju Tsu-Ming Liu Yeh-Lin Chu Chuang-Chi Chiou Bin-Jung Tsai Te-Chi Hsiao Chen, G. Pin-Huan Hsu Chih-Ming Wang Chun-Chia Chen Hue-Min Lin Chia-Yun Cheng Min-Hao Chiu Sheng-Jen Wang Jiun-Yuan Wu Yuan-Chun Lin Yung-Chang Chang Chung-Hung Tsai
Copyright Year	2012
Abstract	a 3D Blu-ray-compliant multimedia processor integrating video decoder, display and graphic engines is presented. To cope with the bandwidth/cost-starved Blu-ray system, this design exploits the time-sharing techniques, leading to 31.3% and 29.1% of area reduction in display and decoder parts. Moreover, a graphic and on-screen-display hardwired handshake effectively reduces the DRAM space by 40%. A smart graphic command removal eliminates the redundant memory accesses by 14%. For 3D Blu-ray playback requirements, stereo full-HD video decoding, 24Hz display, and stereoscopic graphic UI are realized under the frequency of 333MHz, 148MHz, and 333MHz, respectively. This test chip is fabricated in 40nm CMOS process with core area of 3.92mm2 and power dissipation of 124.1mW.
Starting Page	776
Ending Page	781
File Size	616042
Page Count	6
File Format	PDF
ISBN	9781467316590
ISSN	19457871
DOI	10.1109/ICME.2012.81
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2012-07-09
Publisher Place	Australia
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Graphics Decoding Streaming media Engines Random access memory Program processors Bandwidth Display 3D Blu-ray H.264 Graphic
Content Type	Text
Resource Type	Article

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