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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Peltier, J. Hansford, W. Gauthier, C. Lomax, R. Nauna, M. Parakh, P. Stetson, S. |
| Copyright Year | 1997 |
| Description | Author affiliation: Information Sci. Inst., Marina del Rey, CA, USA (Peltier, J.) |
| Abstract | The MCM Designers' Access Service (MIDAS) allows designers to obtain low cost, prototype and small quantities of MCMs. MIDAS low cost price structure comes from a multi-project environment where the customers share tooling and substrate manufacturing costs. The service acts as a technology enabler by supplying the designer with an interface "transparent" to the fabricator and common to multiple vendors. By completing front-end foundry tasks such as data preparation and mask fabrication and by grouping multiple users together on a run, MIDAS offers a low-cost prototype and small quantity service. Utilization of certain design guidelines module footprint size and I/O ring, layer stacking and number of layers and MIDAS supplied standard packages allow the user ample flexibility when designing a module and provides a comprehensive design environment. To date, MIDAS has accepted designs from commercial, military, and educational/research institutions. This paper presents an example of a module that pushes the current MCM-D technology to an extreme limit. The design was done at the University of Michigan and fabricated at MicroModule Systems in Cupertino, CA. It represents a joint design effort amongst the University of Michigan, Motorola, and Cascade Design Automation. It includes a selection of Mayo Foundation Standard Test Structures and six custom designed CGaAs chips fabricated by Motorola. This module is a technology evaluation vehicle that aims to characterize the MCM interconnect and driver-receiver pairs for signal integrity, and evaluate the design methodology in Motorola CGaAs (tm). A clock generator drives two pairs of serial-to-parallel and parallel-to-serial shift-registers at frequencies up to 1 GHz. One chip controls an unterminated databus which will be probed at one end. This MCM is the first of three MCM designs planned in the development of a 1 GHz clock processor which will execute a subset of the PowerPC (tm) instruction set selected to optimize performance in GaAs. This paper discusses MIDAS' role in fabricating and assembling the module, the design effort among the parties listed above and the module's functionality. |
| Starting Page | 43 |
| Ending Page | 47 |
| File Size | 628359 |
| Page Count | 5 |
| File Format | |
| ISBN | 0780337875 |
| DOI | 10.1109/ICMCM.1997.581144 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 1997-04-02 |
| Publisher Place | USA |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Gallium arsenide Costs Prototypes Clocks Manufacturing Foundries Fabrication Guidelines Stacking Packaging |
| Content Type | Text |
| Resource Type | Article |
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