NDLI: Building parallel simulations from serial simulators

Content Provider	IEEE Xplore Digital Library
Author	Heidelberger, P. Nicol, D.
Copyright Year	1996
Description	Author affiliation: IBM Thomas J. Watson Res. Center, Yorktown Heights, NY, USA (Heidelberger, P.)
Abstract	In order for parallel discrete event simulation (PDES) to have practical impact, PDES tools must hide the complexities of time synchronisation from users and provide capabilities approaching those of industrial quality serial simulators. Typically, PDES tools have been started from scratch thereby requiring a modeler to learn a new and unfamiliar modeling tool. This note describes a parallel simulation tool, the Utilitarian Parallel Simulator, U.P.S. that is distinguished from the above mentioned tools in that it is built on top of an existing, industrial quality serial simulator, CSIM. U.P.S. extends the standard CSIM modeling language by providing a simple and natural mechanism for submodels running on different processors to communicate with one another. The user need not be concerned with time synchronisation, save for specifying which algorithm to use, nor need the user make calls to a low level interprocessor communications library (e.g. a message-passing library such as MPI). U.P.S. was implemented without making any changes to the existing CSIM simulation engine. As such, it implements conservative time synchronisation algorithms. As CSIM has been ported to many uniprocessor platforms, and since U.P.S. is implemented using the MPI standard, U.P.S. is potentially portable to many multiple processor systems. It has been tested and run on two such platforms: the IBM SP2 and the Intel Paragon.
Starting Page	2
Ending Page	4
File Size	276539
Page Count	3
File Format	PDF
ISBN	0818672358
DOI	10.1109/MASCOT.1996.500986
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1996-02-01
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Packaging Computational modeling Discrete event simulation Computer simulation Libraries NASA Computer science Educational institutions Computer industry Communication standards
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
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8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in