NDLI: A Study of Center Field Stripe Yield Loss Mechanism

Content Provider	IEEE Xplore Digital Library
Author	Maurya, A. Bin Manaf, M.J. Abdul Rahman, Z. Sim Jit-Shen Chong Seng Ong Thung Beng Joo
Copyright Year	2006
Description	Author affiliation: Silterra Sdn. Bhd., Kulim (Maurya, A.; Bin Manaf, M.J.; Abdul Rahman, Z.; Sim Jit-Shen; Chong Seng Ong; Thung Beng Joo)
Abstract	Detection of killer defects is critical to improving yields in VLSI fabrication. Bright and dark-field inspection tools detect both killer and non-killer defects, and in some cases a high level of nuisance defects may adversely affect the ability to monitor and eliminate the real ones that have a detrimental impact on device yield. E-beam inspection tools take advantage of a phenomenon referred to as voltage contrast, and can differentiate between grounded and floating structures, thus detecting electrical killer defects. A particularly useful application of e-beam inspection is the detection of highly resistive or not-fully opened vias. Finding these types of failures with standard bright or dark-field inspection tools is extremely difficult, given the high aspect ratio and small width of typical vias. Figures showed the basic principle of e-beam analysis for vias. The sample is subjected to the analysis after via etch and barrier deposition. Vias that are fully open have good electrical connection to ground, and appear dark. Vias that are not properly open because of for example, residual dielectric material at the bottom, are electrically floating, and appear bright. This paper reports on a problem with one of the Silterra devices that suffered from sporadic cases of yield loss affecting dies on the center column of the 3times3 reticle field. Vertical stripes of failed dies would thus appear on the wafer sort maps. The failure bin (Bin 60) indicated a problem with the SRAM portion of the device. Based on the suspicion of a Vial problem, e-beam analysis was used to investigate via integrity. The motivation of this work was to find the root cause of the problem and implement a permanent solution
Starting Page	179
Ending Page	182
File Size	3067399
Page Count	4
File Format	PDF
ISBN	1424402050
DOI	10.1109/IPFA.2006.251025
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2006-07-03
Publisher Place	Singapore
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Inspection Electrons Voltage Etching Very large scale integration Fabrication Monitoring Boosting Dielectric materials Virtual colonoscopy
Content Type	Text
Resource Type	Article

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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