NDLI: Dislocation density reduction during impurity gettering in multicrystalline silicon

Content Provider	IEEE Xplore Digital Library
Author	Choi, H. J. Bertoni, M. I. Hofstetter, J. Fenning, D. P. Powell, D. M. Castellanos, S. Buonassisi, T.
Copyright Year	2012
Description	Author affiliation: Massachusetts Institute of Technology, Cambridge, 02139 USA (Choi, H. J.; Bertoni, M. I.; Hofstetter, J.; Fenning, D. P.; Powell, D. M.; Castellanos, S.; Buonassisi, T.)
Abstract	Isothermal annealing above 1250 °C has been reported to reduce the dislocation density in multicrystalline silicon (mc-Si), presumably by pairwise dislocation annihilation. However, this high-temperature process may also cause significant impurity contamination, canceling out the positive effect of dislocation density reduction on cell performance. Here, efforts are made to annihilate dislocations in mc-Si in temperatures as low as 820 °C, with the assistance of an additional driving force to stimulate dislocation motion. A reduction of more than 60% in dislocation density is observed for mc-Si containing intermediate concentrations of certain metallic species after P gettering at 820 °C. While the precise mechanism remains in discussion, available evidence suggests that the net unidirectional flux of impurities in the presence of a gettering layer may cause dislocation motion, leading to dislocation density reduction. Analysis of minority carrier lifetime as a function of dislocation density suggests that lifetime improvements after P diffusion in these samples can be attributed to the combined effects of dislocation density reduction and impurity concentration reduction. These findings suggest there may be mechanisms to reduce dislocation densities at standard solar cell processing temperatures.
Starting Page	1
Ending Page	10
File Size	1729266
Page Count	10
File Format	PDF
DOI	10.1109/PVSC-Vol2.2012.6656733
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2012-06-03
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Gettering Impurities Annealing Silicon Contamination Charge carrier lifetime Surface treatment P gettering Al gettering dislocation density dislocation impurity interaction multicrystalline silicon
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in