NDLI: Fast and cycle-accurate modeling of a multicore processor

Content Provider	IEEE Xplore Digital Library
Author	Khan, A. Vijayaraghavan, M. Boyd-Wickizer, S. Arvind, A.
Copyright Year	2012
Description	Author affiliation: Computer Science and Artificial Intelligence Laboratory, Massachusetts Institute of Technology, Cambridge, USA (Khan, A.; Vijayaraghavan, M.; Boyd-Wickizer, S.; Arvind, A.)
Abstract	An ideal simulator allows an architect to swiftly explore design alternatives and accurately determine their impact on performance. Design exploration requires simulators to be easily modifiable, and accurate performance estimates require detailed models. Unfortunately, detailed modeling not only impacts the ease with which a simulator can be modified, but also the speed at which it can be executed, resulting in fidelity being traded for simulation speed. Although FPGA-based simulators have dramatically higher speed than software simulators, sacrificing fidelity is still common. In this paper we present Arete, an FPGA-based processor simulator, which offers high performance along with accuracy and modifiability. We begin with a cycle-level specification of a multicore architecture which includes realistic in-order cores and detailed models of shared, coherent memory and on-chip network. We then describe how this specification is implemented faithfully and efficiently on FPGAs. Arete delivers a performance of up to 11 MIPS per core. We run a subset of the PARSEC benchmark suite on top of off-the-shelf SMP Linux, and achieve an average performance of 55 MIPS for an 8-core model.We also describe two significant architectural explorations: one involving three different branch predictors and the other requiring major modifications to the cache-coherence protocol.
Starting Page	178
Ending Page	187
File Size	232321
Page Count	10
File Format	PDF
ISBN	9781467311434
e-ISBN	9781467311465
e-ISBN	9781467311458
DOI	10.1109/ISPASS.2012.6189224
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2012-04-01
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Field programmable gate arrays Random access memory Multicore processing Debugging Registers Tiles
Content Type	Text
Resource Type	Article

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