NDLI: RAMP: research accelerator for multiple processors - a community vision for a shared experimental parallel HW/SW platform

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RAMP: research accelerator for multiple processors - a community vision for a shared experimental parallel HW/SW platform

Simulation sampling with live-points

Accelerating architectural exploration using canonical instruction segments

Branch trace compression for snapshot-based simulation

Critical path analysis of the TRIPS architecture

Characterizing the branch misprediction penalty

Revisiting the performance impact of branch predictor latencies

Evaluating the efficacy of statistical simulation for design space exploration

Comparing simulation techniques for microarchitecture-aware floorplanning

A statistical multiprocessor cache model

Power efficient resource scaling in partitioned architectures through dynamic heterogeneity

Compiler-based adaptive fetch throttling for energy-efficiency

Modeling TCAM power for next generation network devices

Quantitative system design

Comparing multinomial and k-means clustering for SimPoint

Considering all starting points for simultaneous multithreading simulation

Automatic testcase synthesis and performance model validation for high performance PowerPC processors

Improved stride prefetching using extrinsic stream characteristics

Friendly fire: understanding the effects of multiprocessor prefetches

MESA: reducing cache conflicts by integrating static and run-time methods

Performance modeling and prediction for scientific Java applications

Assessing the impact of reactive workloads on the performance of Web applications

Workload sanitation for performance evaluation

ATTILA: a cycle-level execution-driven simulator for modern GPU architectures

Acquisition and evaluation of long DDR2-SDRAM access sequences

Aestimo: a feedback-directed optimization evaluation tool

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RAMP: research accelerator for multiple processors - a community vision for a shared experimental parallel HW/SW platform

Content Provider	IEEE Xplore Digital Library
Author	Patterson, D.A.
Copyright Year	2006
Description	Author affiliation: California Univ., Berkeley, CA, USA (Patterson, D.A.)
Abstract	Summary form only given. The vast majority of computer architects believe the future of the microprocessor is hundreds to thousands of processors ("cores") on a chip. Given such widespread agreement, it's surprising how much research remains to be done in algorithms, computer architecture, networks, operating systems, file systems, compilers, programming languages, applications, and so on to realize this vision. Fortunately, Moore's law has not only enabled dense multi-core chips, it has also enabled extremely dense FPGAs. Today, one to two dozen soft cores can be programmed into a single FPGA. With multiple FPGAs on a board and multiple boards in a system, 1000-processor designs can be economically and rapidly explored. To make this happen, however, requires a significant amount of infrastructure in hardware, software, and what we call "gateware", the register-transfer level models that fill the FGPAs. By using the Berkeley Emulation Engine boards that were created for other purposes, the hardware is already done. A group of architects plan to design the gateware, create this infrastructure, and share the results in an open-source fashion so that every institution could have their own. Such a system would not just invigorate multiprocessors research in the architecture community. Since processors cores can run at 100 to 200 MHz, a large scale multiprocessor would be fast enough to run operating systems and large programs at speeds sufficient to support software research. Moreover, there is a new generation of FPGAs every 18 months with capacity for twice as many cores and run them faster, so future multiboard FPGA systems are even more attractive. Hence, we believe such a system would accelerate research across all the fields that touch multiple processors. Thus the acronynm RAMP, for Research Accelerator for Multiple Processors. RAMP has the potential to transform the parallel computing community in computer science from a simulation-driven to a prototype-driven discipline, leading to rapid iteration across interfaces of the many fields of multiple processors, and thereby moving much more quickly to a parallel foundation for large-scale computer systems research in the 21st century.
Sponsorship	IEEE Comput. Soc
File Size	34824
File Format	PDF
ISBN	1424401860
DOI	10.1109/ISPASS.2006.1620784
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2006-03-19
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

Project Summary for NSF Solicitation 04-588 CRI: RAMP: Research Accelerator for Multiple Processors- A Community Vision for a Shared Experimental Parallel HW/SW Platform

Using HW/SW Codesign for Deep Neural Network Hardware Accelerator Targeting Low-Resources Embedded Processors

A HW/SW Co-design of Execution Migration for Shared-ISA Heterogeneous Chip Multiprocessors

Speculative dynamic vectorization for HW/SW co-designed processors

Warm-Up Simulation Methodology for HW/SW Co-Designed Processors

Accurate off-line phase classification for HW/SW co-designed processors

HW/SW Co-Design of a Specific Accelerator for Robotic Computer Vision

HW/SW Co-Design of a Specific Accelerator for Robotic Computer Vision

Xilinx system generator based hw components for rapid prototyping of computer vision sw/hw systems*.

RAMP: research accelerator for multiple processors - a community vision for a shared experimental parallel HW/SW platform

Similar Documents

Project Summary for NSF Solicitation 04-588 CRI: RAMP: Research Accelerator for Multiple Processors- A Community Vision for a Shared Experimental Parallel HW/SW Platform

Using HW/SW Codesign for Deep Neural Network Hardware Accelerator Targeting Low-Resources Embedded Processors

A HW/SW Co-design of Execution Migration for Shared-ISA Heterogeneous Chip Multiprocessors

Speculative dynamic vectorization for HW/SW co-designed processors

Warm-Up Simulation Methodology for HW/SW Co-Designed Processors

Accurate off-line phase classification for HW/SW co-designed processors

HW/SW Co-Design of a Specific Accelerator for Robotic Computer Vision

HW/SW Co-Design of a Specific Accelerator for Robotic Computer Vision

Xilinx system generator based hw components for rapid prototyping of computer vision sw/hw systems*.

RAMP: research accelerator for multiple processors - a community vision for a shared experimental parallel HW/SW platform