NDLI: Realities of Multi-Core CPU Chips and Memory Contention

Content Provider	IEEE Xplore Digital Library
Author	Barker, D.P.
Copyright Year	2009
Abstract	The relationship between the cpu and memory has always been of prime importance in the HPC eco-sphere. Current trends in multi-core chip designs look to alarmingly upset the balance of that relationship. The number of cpus in a chip is growing, while the interface to memory stays relatively static. How are we to adapt our software to this new paradigm in order to maximize the utility of those extra cpus?The answer, of course, depends on your code. We show an example of some simple tools and metrics that identify the points in a parallel application where the memory resource is over-stressed. Surprisingly,in our sample application, these points are not necessarily the most time-consuming ones in the case of a non-multi-core version. Careful removal of some parallel regions shows the potential for improved scalability on multi-core systems, as the benefit of the multi-core portions of the code outweigh the relatively small areas where parallelism is now removed.Application of this technique should be broadly applicable to the overall ecology of parallel applications migrating to the multi-core paradigm.
Starting Page	446
Ending Page	453
File Size	329619
Page Count	8
File Format	PDF
ISBN	9780769535449
ISSN	10666192
DOI	10.1109/PDP.2009.65
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2009-02-18
Publisher Place	Germany
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Linux Scalability Testing Power system interconnection Sun Chip scale packaging Application software Parallel programming Biological system modeling Environmental factors performance analysis multi-core oprofile op_scope memory contention
Content Type	Text
Resource Type	Article

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
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3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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Linux multi-core scalability (2009).

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