NDLI: Address-Value Decoupling for Early Register Deallocation

Content Provider	IEEE Xplore Digital Library
Author	Balkan, D. Sharkey, J. Ponomarev, D. Aggarwal, A.
Copyright Year	2006
Description	Author affiliation: Dept. of Comput. Sci., State Univ. of New York, Binghamton, NY (Balkan, D.; Sharkey, J.; Ponomarev, D.)
Abstract	We propose a series of aggressive register deallocation mechanisms to reduce the register file pressure and increase the parallelism exploited by superscalar microprocessors. Our techniques are based on a key observation that a register value can be temporarily decoupled from the register identifier. Specifically, even if a physical register is deallocated, the value is still available in the register and can be read by the dependent instructions until the register is overwritten. In these situations, we can effectively overlap the consumption of the produced register value and partial processing of the instruction that gets the same register reassigned to it. In this paper, we propose several realizations of the address-value decoupling idea and discuss their implications on the performance. Our most aggressive scheme achieves an average IPC speedup of 14.6% across simulated SPEC 2000 benchmarks
Sponsorship	IEEE CPS
Starting Page	337
Ending Page	346
File Size	189455
Page Count	10
File Format	PDF
ISBN	0769526365
ISSN	01903918
DOI	10.1109/ICPP.2006.20
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2006-08-14
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Registers Parallel processing Clocks Writing Computer science Microprocessors Microarchitecture Data mining Read-write memory Delay
Content Type	Text
Resource Type	Article

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