NDLI: A study of partitioned vector register files

Content Provider	IEEE Xplore Digital Library
Author	Lee, C.G. Smith, J.E.
Copyright Year	1992
Description	Author affiliation: Dept. of Electr. Eng., Toronto Univ., Ont., Canada (Lee, C.G.)
Abstract	The authors study partitioned video register files, where multiple vector registers are connected by a pair of buses to a set of functional units. Although less costly to implement, this alternative organization places some restrictions on accessing vector registers, thus potentially degrading processor performance. To circumvent this restrictive access, the authors develop a heuristic algorithm for assigning vector registers in a partitioned vector register file. By compiling a set of benchmarks with the proposed assignment algorithm, the authors generated data showing that the performance of this alternative register organization is comparable to that of a traditional one. Moreover, the data show that eight pairs of buses are adequate for a Cray Y-MP vector processor. If each pair of buses services two vector registers, for a total of 16, the algorithm successfully assigns 94% of the benchmark loops. Using 32 vector registers raises this percentage to 97%.
Starting Page	94
Ending Page	103
File Size	779914
Page Count	10
File Format	PDF
ISBN	0818626305
DOI	10.1109/SUPERC.1992.236706
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1992-11-16
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Registers Counting circuits Read-write memory Costs Vector processors Degradation Writing Clocks Processor scheduling Data buses
Content Type	Text
Resource Type	Article

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