NDLI: A distributed multiple-SIMD processor in memory

Content Provider	IEEE Xplore Digital Library
Author	Rangan, K.K. Abu-Ghazaleh, N.B. Wilsey, P.A.
Copyright Year	2001
Description	Author affiliation: Experimental Comput. Lab., Cincinnati Univ., OH, USA (Rangan, K.K.)
Abstract	The integration of processing and DRAM offers a potential solution to the memory bottleneck problem. The bandwidth available within the chip is several orders of magnitude higher than that at the memory bus with a lower access time. As workloads shift towards data-intensive/multimedia applications, the wide bandwidth can be effectively utilized by harnessing the parallelism available in these applications. There are difficult challenges in developing architectures and programming models that expose the available bandwidth to the application. This paper presents the design of an intelligent memory based on a distributed data-parallel architecture with limited support for control parallelism. We investigate some of the relevant design issues and evaluate the success of such an architecture in supporting data-intensive applications. The design is evaluated as a stand-alone system, and also as a co-processor acting as a memory access filter. A cycle-accurate simulator is developed and used to study the performance of the architecture for data-intensive applications. The performance is compared against that of a modern superscalar processor.
Sponsorship	Int. Assoc. Comput. & Commun
Starting Page	507
Ending Page	514
File Size	764224
Page Count	8
File Format	PDF
ISBN	0769512577
ISSN	01903918
DOI	10.1109/ICPP.2001.952098
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2001-09-03
Publisher Place	Spain
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Bandwidth Parallel processing Computer architecture Logic programming Laboratories Random access memory Coprocessors Application software Microprocessors Plasma welding
Content Type	Text
Resource Type	Article

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
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3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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