NDLI: Register-sensitive software pipelining

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Proceedings 13th International Parallel Processing Symposium and 10th Symposium on Parallel and Distributed Processing. IPPS/SPDP 1999

Proceedings of the First Merged International Parallel Processing Symposium and Symposium on Parallel and Distributed Processing

Proceedings of the First Merged International Parallel Processing Symposium and Symposium on Parallel and Distributed Processing

Nearly optimal algorithms for broadcast on d-dimensional all-port and wormhole-routed torus

Minimizing total communication distance of a time-step optimal broadcast in mesh networks

Hiding communication latency in data parallel applications

Protocols for non-deterministic communication over synchronous channels

Broadcast-efficient algorithms on the coarse-grain broadcast communication model with few channels

Optimal all-to-some personalized communication on hypercubes

Compiler optimization of implicit reductions for distributed memory multiprocessors

Local enumeration techniques for sparse algorithms

Optimizing data scheduling on processor-in-memory arrays

An expression-rewriting framework to generate communication sets for HPF programs with block-cyclic distribution

A generalized framework for global communication optimization

Evaluation of compiler and runtime library approaches for supporting parallel regular applications

Preliminary results from a parallel MATLAB compiler

Jacobi orderings for multi-port hypercubes

Automatic differentiation for message-passing parallel programs

Processor lower bound formulas for array computations and parametric Diophantine systems

A flexible class of parallel matrix multiplication algorithms

Caching-efficient multithreaded fast multiplication of sparse matrices

Permutation capability of optical multistage interconnection networks

HIPIQS: a high-performance switch architecture using input queuing

On the bisection width and expansion of butterfly networks

Multiprocessor architectures using multi-hop multi-OPS lightwave networks and distributed control

Distributed, dynamic control of circuit-switched Banyan networks

A case for aggregate networks

An enhanced Co-scheduling method using reduced MS-state diagrams

Predicated software pipelining technique for loops with conditions

The generalized lambda test

Experimental study of compiler techniques for NUMA machines

Register-sensitive software pipelining

Analyzing the individual/combined effects of speculative and guarded execution on a superscalar architecture

NOW based parallel reconstruction of functional images

An improved output-size sensitive parallel algorithm for hidden-surface removal for terrains

Design, implementation and evaluation of parallel pipelined STAP on parallel computers

The VEGA moderately parallel MIMD, moderately parallel SIMD, architecture for high performance array signal processing

Medical image processing and visualization on heterogenous clusters of symmetric multiprocessors using MPI and POSIX threads

A quantitative code analysis of scientific systolic programs: DSP vs. matrix algorithms

Tree-based multicasting in wormhole-routed irregular topologies

NoWait-RPC: extending ONC RPC to a fully compatible message passing system

Efficient barrier synchronization mechanism for the BSP model on message-passing architectures

Performance and experience with LAPI-a new high-performance communication library for the IBM RS/6000 SP

Total-exchange on wormhole k-ary n-cubes with adaptive routing

Managing concurrent access for shared memory active messages

Design and implementation of a parallel I/O runtime system for irregular applications

Using PI/OT to support complex parallel I/O

Code transformations for low power caching in embedded multimedia processors

Memory hierarchy management for iterative graph structures

High-performance external computations using user-controllable I/O

Pin-down cache: a virtual memory management technique for zero-copy communication

Synthesis of a systolic array genetic algorithm

Vector prefix and reduction computation on coarse-grained, distributed-memory parallel machines

Solving the maximum clique problem using PUBB

A scalable VLSI architecture for binary prefix sums

Emulating direct products by index-shuffle graphs

A comparative study of five parallel genetic algorithms using the traveling salesman problem

A new self-routing multicast network

Optimal contention-free unicast-based multicasting in switch-based networks of workstations

Multicasting and broadcasting in large WDM networks

Optimally locating a structured facility of a specified length in a weighted tree network

Deterministic routing of h-relations on the multibutterfly

An efficient counting network

Partitioned schedules for clustered VLIW architectures

Dynamic processor allocation with the Solaris operating system

Thread-based vs event-based implementation of a group communication service

Performance sensitivity of space-sharing processor scheduling in distributed-memory multicomputers

Efficient fine-grain thread migration with active threads

Clustering and reassignment-based mapping strategy for message-passing architectures

Asymptotically optimal randomized tree embedding in static networks

Resource placements in 2D tori

An O((log log n)/sup 2/) time convex hull algorithm on reconfigurable meshes

Toward a universal mapping algorithm for accessing trees in parallel memory systems

Sharing random bits with no process coordination

Lower bounds on communication loads and optimal placements in torus networks

Impact of switch design on the application performance of cache-coherent multiprocessors

Parallel tree building on a range of shared address space multiprocessors: algorithms and application performance

Configuration independent analysis for characterizing shared-memory applications

Experimental validation of parallel computation models on the Intel Paragon

Comparing the optimal performance of different MIMD multiprocessor architectures

The design of COMPASS: an execution driven simulator for commercial applications running on shared memory multiprocessors

An efficient RMS admission control and its application to multiprocessor scheduling

Guidelines for data-parallel cycle-stealing in networks of workstations

Low memory cost dynamic scheduling of large coarse grain task graphs

Benchmarking the task graph scheduling algorithms

A performance evaluation of CP list scheduling heuristics for communication intensive task graphs

Utilization and predictability in scheduling the IBM SP2 with backfilling

High performance data mining using data cubes on parallel computers

An efficient parallel algorithm for high dimensional similarity join

Sorting on clusters of SMPs

An AT/sup 2/ optimal mapping of sorting onto the mesh connected array without comparators

ScalParC: a new scalable and efficient parallel classification algorithm for mining large datasets

Improved concurrency control techniques for multi-dimensional index structures

DEEP: a development environment for parallel programs

Rapid development of real-time systems using RTExpress/sup TM/

Evaluating ASIC, DSP, and RISC architectures for embedded applications

The effect of the router arbitration policy on the scalability of ServerNet/sup TM/ topologies

WILDFIRE(TM) heterogeneous adaptive parallel processing systems

ACEcard/sup TM/: a high-performance architecture for run-time reconfiguration

A hardware/software co-design system using configurable computing technology

A clustered approach to multithreaded processors

C++ expression template performance issues in scientific computing

Aggressive dynamic execution of multimedia kernel traces

Performance prediction in production environments

Predicting the running times of parallel programs by simulation

Compile-time synchronization optimizations for software DSMs

An efficient logging scheme for lazy release consistent distributed shared memory systems

Update protocols and iterative scientific applications

Characterizations for Java memory behavior

Locality and performance of page- and object-based DSMs

Optimistic synchronization of mixed-mode simulators

Airshed pollution modeling: a case study in application development in an HPF environment

Design of a FEM computation engine for real-time laparoscopic surgery simulation

SIMD and mixed-mode implementations of a visual tracking algorithm

The implicit pipeline method

Rendering computer animations on a network of workstations

Hyper-butterfly network: a scalable optimally fault tolerant architecture

Algorithms exploiting spare capacity and tasks laxities for fault detection and location in real-time multiprocessor systems

The robust-algorithm approach to fault tolerance on processor arrays: fault models, fault diameter, and basic algorithms

Fault-tolerant switched local area networks

Trace-driven debugging of message passing programs

Predicate control for active debugging of distributed programs

VPPB-a visualization and performance prediction tool for multithreaded Solaris programs

Parallel performance visualization using moments of utilization data

Optimizing parallel applications for wide-area clusters

Prioritized token-based mutual exclusion for distributed systems

Adaptive quality equalizing: high-performance load balancing for parallel branch-and bound across applications and computing systems

Memory space representation for heterogeneous network process migration

Index of authors

Proceedings 11th International Parallel Processing Symposium

Proceedings of International Conference on Parallel Processing

Proceedings of 9th International Parallel Processing Symposium

Proceedings of 8th International Parallel Processing Symposium

[1993] Proceedings Seventh International Parallel Processing Symposium

Proceedings Sixth International Parallel Processing Symposium

[1991] Proceedings. The Fifth International Parallel Processing Symposium

Register-sensitive software pipelining

Content Provider	IEEE Xplore Digital Library
Author	Dani, A.K. Janaki Ramanan, V. Govindarajan, R.
Copyright Year	1998
Description	Author affiliation: Veritas Software India Pvt. Ltd., Pune, India (Dani, A.K.)
Abstract	We propose an integrated approach for register-sensitive software pipelining. In this approach, the heuristics proposed in the stage scheduling method of A.E. Eichenberger and E.S. Davidson (1995) are integrated with the iterative scheduling method to obtain schedules with high initiation rate and low register requirements. The performance of our integrated software pipelining method was analyzed for a large number of loops taken from a variety of scientific benchmark programs. Our studies reveal that the stage scheduling heuristics facilitate better performance benefits when applied at the scheduling time, resulting in significant performance improvement over both the stage scheduling method and the slack scheduling method.
Starting Page	194
Ending Page	198
File Size	544883
Page Count	5
File Format	PDF
ISBN	0818684046
ISSN	10637133
DOI	10.1109/IPPS.1998.669910
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1998-03-30
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Pipeline processing Iris Scheduling algorithm Modems Educational institutions Supercomputers Iterative methods
Content Type	Text
Resource Type	Article

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