NDLI: Efficient two-level mesh based simulation of PRAMS

Content Provider	IEEE Xplore Digital Library
Author	Forsell, M. Leppanen, V. Penttonen, M.
Copyright Year	1996
Description	Author affiliation: Dept. of Comput. Sci., Joensuu Univ., Finland (Forsell, M.)
Abstract	We consider time-processor optimal simulations of PRAM models on coated block meshes. A coated block mesh consists of n-processor blocks and /spl pi//spl times//spl pi/ or /spl radic/(/spl pi/)/spl times//spl radic/(/spl pi/)/spl times//spl radic/(/spl pi/) router blocks. The router blocks form a 2-dimensional or a 3-dimensional regular mesh, and the processor and memory blocks are located on the surface of the block mesh. As a generalization of the coated mesh, the 2-dimensional and 3-dimensional coated block meshes simulate EREW, CREW, and CRCW PRAM models time-processor optimally with moderate simulation cost. Using proper amount of parallel slackness, the cost can be decreased clearly below 2 routing steps per simulated PRAM processor. The coated block mesh is actually an instance of a more general two-level construction technique, which uses a seemingly inefficient but scalable solution on top of a non-scalable but efficient solution. Within blocks (chips) brute force techniques are applied, whereas the mesh structure on top makes the whole construction modular, simple, and scalable. The parameter /spl pi/ provides a method to balance the construction with respect to the two techniques. Keywords: PRAM, shared memory machine, simulation, time-processor optimal, mesh, interconnection network.
Starting Page	29
Ending Page	35
File Size	731665
Page Count	7
File Format	PDF
ISBN	0818674601
ISSN	10874089
DOI	10.1109/ISPAN.1996.508957
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1996-06-12
Publisher Place	China
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Phase change random access memory Routing Machinery Yarn Costs Hypercubes Scalability Hardware Neural networks Sparse matrices
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

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