NDLI: POERS: a performance-oriented energy reduction scheduling technique for a high-performance MPSoC architecture

Content Provider	IEEE Xplore Digital Library
Author	Slo-Li Chu
Copyright Year	2005
Description	Author affiliation: Dept. of Inf. & Comput. Eng., Chung Yuan Christian Univ., Chung-li, Taiwan (Slo-Li Chu)
Abstract	Continuous improvements in semiconductor technology are supporting new classes of multi-processor system-on-a-chip (MPSoC) architectures that combine extensive processing logic with high-density memory. Such architectures are generally colled processor-in-memory (PIM) or intelligent memory (I-RAM) and can support high-performance computing by reducing the performance gap between the processor and the memory. The PIM architecture combines various processors in a single chip. These processors are characterized by their computation, memory-access, and power consumption capabilities. Therefore, a novel parallelizing system, SAGE II, has be developed to identify their capabilities and dispatch the most appropriate jobs to them in order to exploit the advantages of PIM architectures. This paper provides a new low-power transformation mechanism, called performance-oriented energy reduction scheduling (POERS), to extend the capability of SAGE II system. It can reduce the energy consumption for the processor-in-memory system without losing execution performance. The detailed POERS transformation technique is presented later. The experimental results of several benchmarks are also discussed.
Sponsorship	IEEE Comput. Soc. TCDP and TCPP Fukuoka Inst. of Technol. (FIT)
Starting Page	699
Ending Page	702
File Size	215833
Page Count	4
File Format	PDF
ISBN	0769522815
ISSN	15219097
DOI	10.1109/ICPADS.2005.238
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2005-07-20
Publisher Place	Japan
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Computer architecture Processor scheduling Random access memory Energy consumption High performance computing System-on-a-chip Logic Memory architecture Delay Embedded computing Energy Reduction POERS SAGE II MPSoC Processor-in-Memory
Content Type	Text
Resource Type	Article
Subject	Hardware and Architecture

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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