NDLI: Bottleneck-free interconnect and IO subsystem in SPAX

Content Provider	IEEE Xplore Digital Library
Author	Kangwoo Lee Woo-Jong Han Dubois, M.
Copyright Year	1997
Description	Author affiliation: Dept. of Electr. Eng. Syst., Univ. of Southern California, Los Angeles, CA, USA (Kangwoo Lee)
Abstract	The performance of parallel systems under commercial applications strongly depend on the speeds of IO subsystems and interconnects. Any single bottleneck in there hinder one from fully taking advantages of today's faster CPUs and better instruction architectures. Therefore, configuring bottleneck-free IO subsystems and interconnects is essential. In this paper we considered IO subsystem and interconnect in SPAX system. When the SPAX's IO subsystem is lightly equipped, the first bottleneck appears at disk drives. Although the disk bottleneck can be removed by putting more disks, another bottleneck was detected at the data buffer which is the first component in communication path. That is to say, all components in IO subsystems and interconnects must be sufficiently equipped, simultaneously, to thoroughly eliminate the bottleneck. We could reach a cost-effective bottleneck-free configuration of SPAX by making use of its flexible hardware design. The simulation results of SPAX then show significant performance gain from faster CPUs with better instruction architectures.
Starting Page	524
Ending Page	533
File Size	961360
Page Count	10
File Format	PDF
ISBN	0818682272
DOI	10.1109/ICPADS.1997.652595
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1997-12-10
Publisher Place	South Korea
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Hardware Benchmark testing Neck Disk drives Computer aided instruction Parallel architectures Scientific computing Concurrent computing Electronic equipment testing Computer buffers
Content Type	Text
Resource Type	Article

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